HD49340HNP

更新时间： 2024-02-13 03:21:58

品牌	Logo	应用领域
瑞萨 - RENESAS		转换器模数转换器
页数	文件大小	规格书
22页	232K
描述
CDS/PGA & 10-bit A/D Converter

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中文翻译

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技术参数
数据手册
替代型号

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HD49340HNP 技术参数

生命周期：	Transferred	零件包装代码：	QFN
包装说明：	QFN-36	针数：	36
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.59
Is Samacsys：	N	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-XQCC-N36	长度：	6.2 mm
模拟输入通道数量：	1	位数：	10
功能数量：	1	端子数量：	36
最高工作温度：	85 °C	最低工作温度：	-20 °C
输出位码：	BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	UNSPECIFIED	封装代码：	VQCCN
封装等效代码：	LCC36,.25SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, VERY THIN PROFILE	电源：	3 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	0.95 mm	子类别：	Other Converters
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	6.2 mm
Base Number Matches：	1

HD49340HNP 数据手册

HD49340NP/HNP

2. PGA Circuit

The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain

using 8 bits of register.

The equation below shows how the gain changes when register value N is from 0 to 255.

In CDSIN mode: Gain = (–2.36 dB + 0.132 dB) × N (LOG linear).

In ADCIN mode: Gain = (0.57 times + 0.00446 times) × N (linear).

Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

3. Automatic Offset Calibration Function and Black-Level Clamp Data Setting

The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.

The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (14

LSB to 76 LSB) set by register are added and input to the DAC.

The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and

terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Compensation Feedback Function

Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets

(including the CCD offset and the CDSAMP offset) are compensated for.

The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged

by the current DAC (see figure 1).

The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is

the one cycle of the OBP.

∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)

Example:When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop

gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 4 times, 8 times, 16

times, or 32 times by changing the register settings (see table 1). Note that the open-loop differential gain

(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.

The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be

selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 32 LSB, the high-speed lead-in operation continues,

and when the offset error is 32 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4

H, or 8 H depending on the register settings. See table 2.

Table 1 Loop Gain Multiplication Factor during

High-Speed Lead-In Operation

Table 2 High-Speed Lead-In Operation

Cancellation Time

HGain-Nsel

(register settings)

HGstop-Hsel

(register settings)

Multiplication

Factor N

Cancellation

Time

[0]

[1]

[0]

[1]

1 H

2 H

4 H

8 H

5. Pre-Blanking Function

During the PBLK input period, the CDS input operation is separated and protected from the large input signal. The

ADC digital output is fixed to clamp data (14 to 76 LSB).

Rev.1.0 Apr 20, 2004 page 6 of 21

1...3 4 567 8 9...22

中文翻译

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HD49340HNP 替代型号

型号	品牌	替代类型	描述	数据表
HD49340HNP-E	RENESAS	功能相似	暂无描述

与HD49340HNP相关器件

型号	品牌	获取价格	描述	数据表
HD49340HNP-E	RENESAS	获取价格	暂无描述
HD49340NP	RENESAS	获取价格	CDS/PGA & 10-bit A/D Converter
HD49351BP	RENESAS	获取价格	CDS/PGA & 10-bit A/D TG Converter
HD49351BP-E	RENESAS	获取价格	1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA65, FBGA-65
HD49351HBP	RENESAS	获取价格	CDS/PGA & 10-bit A/D TG Converter
HD49404	ETC	获取价格	TV/Video Signal Processor
HD49405	ETC	获取价格
HD49406	ETC	获取价格	MEMORY CONTROLLER
HD49409FS	ETC	获取价格	Picture-in-Picture Circuit
HD49410FS	HITACHI	获取价格	Picture-In-Picture IC, PQFP100, FP-100

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