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HD49351BP-E PDF预览

HD49351BP-E

更新时间: 2024-02-22 10:25:32
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器
页数 文件大小 规格书
29页 330K
描述
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA65, FBGA-65

HD49351BP-E 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:FBGA-65针数:65
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:N最大模拟输入电压:3 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-XBGA-B65
JESD-609代码:e1长度:6 mm
模拟输入通道数量:1位数:10
功能数量:1端子数量:65
最高工作温度:75 °C最低工作温度:-10 °C
输出位码:BINARY输出格式:PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:TFBGA
封装等效代码:BGA64,10X10,20封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH电源:3 V
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.2 mm子类别:Other Converters
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
宽度:6 mmBase Number Matches:1

HD49351BP-E 数据手册

 浏览型号HD49351BP-E的Datasheet PDF文件第2页浏览型号HD49351BP-E的Datasheet PDF文件第3页浏览型号HD49351BP-E的Datasheet PDF文件第4页浏览型号HD49351BP-E的Datasheet PDF文件第5页浏览型号HD49351BP-E的Datasheet PDF文件第6页浏览型号HD49351BP-E的Datasheet PDF文件第7页 
HD49351BP/HBP  
CDS/PGA & 10-bit A/D TG Converter  
REJ03F0110-0100Z  
Rev.1.0  
Jul 06, 2004  
Description  
The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera  
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351  
has deleted the stripe mode, pd_mix mode, and added the 5 – 6 pulse and H_msk2 - 4 as contrasted with HD49335.  
There are address map and timing generator charts besides this specification. May be contacted to our sales department  
if examining the details.  
Functions  
Correlated double sampling  
PGA  
10-bit ADC  
Timing generator  
Operates using only the 3 V voltage  
Corresponds to switching mode of power consumption and operating frequency  
220 mW (Typ), maximum frequency: 36 MHz (HD49351HBP)  
150 mW (Typ), maximum frequency: 25 MHz (HD49351BP)  
ADC direct input mode  
FBGA 65-pin package  
Features  
Suppresses low-frequency noise, which output from CCD by the correlated double sampling.  
The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and  
registers.  
High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.  
PGA, pulse timing, standby mode, etc., is achieved via a serial interface.  
High precision is provided by a 10-bit-resolution A/D converter.  
Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization  
(wave pattern). It is patented by Renesas.  
Timing generator generates the all of pulse which are needed for CCD driving.  
Rev.1.0, Jul 06, 2004, page 1 of 28  

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