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HD49351BP-E

更新时间： 2024-01-12 11:28:46
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器
页数 文件大小 规格书
29页 330K
描述
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA65, FBGA-65

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HD49351BP-E 技术参数

生命周期：Transferred零件包装代码：BGA
包装说明：FBGA-65针数：65
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.65
Is Samacsys：N最大模拟输入电压：3 V
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-XBGA-B65
JESD-609代码：e1长度：6 mm
模拟输入通道数量：1位数：10
功能数量：1端子数量：65
最高工作温度：75 °C最低工作温度：-10 °C
输出位码：BINARY输出格式：PARALLEL, WORD
封装主体材料：UNSPECIFIED封装代码：TFBGA
封装等效代码：BGA64,10X10,20封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH电源：3 V
认证状态：Not Qualified采样并保持/跟踪并保持：SAMPLE
座面最大高度：1.2 mm子类别：Other Converters
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

HD49351BP-E 数据手册

 浏览型号HD49351BP-E的Datasheet PDF文件第3页浏览型号HD49351BP-E的Datasheet PDF文件第4页浏览型号HD49351BP-E的Datasheet PDF文件第5页浏览型号HD49351BP-E的Datasheet PDF文件第7页浏览型号HD49351BP-E的Datasheet PDF文件第8页浏览型号HD49351BP-E的Datasheet PDF文件第9页 
HD49351BP/HBP  
Internal Functions  
Functional Description  
•
CDS input  
CCD low-frequency noise is suppressed by CDS (correlated double sampling).  
The signal level is clamped at 14 LSB to 76 LSB (set by resister: 5 bit 2 LSB step controls) during the OB  
period. *1  
Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2  
ADC input  
•
The center level of the input signal is clamped at 512 LSB (Typ).  
Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57  
times (–4.86 dB) to 5.14 times (14.22 dB). *2  
•
•
•
Automatic offset calibration of PGA and ADC  
DC offset compensation feedback for CCD and CDS  
Pre-blanking  
Digital output is fixed at clamp level  
•
Digital outputs enable function  
Note: 1. It is not covered by warranty when 14 LSB settings  
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.  
Operating Description  
Figure 1 shows CDS/PGA + ADC function block.  
ADC_in  
SP2  
D0 to D9  
PG  
AMP  
10bit  
ADC  
CDS  
AMP  
C2  
CDS_in  
SP1  
Offset  
calibration  
logic  
DAC  
Gain setting  
(register)  
SH  
AMP  
SP1  
C1  
Clamp data  
(register)  
DC offset  
feedback  
logic  
Current  
DAC  
VRT  
BLKFB  
BLKC  
C4  
BLKSH  
OBP  
C3  
Figure 1 CDS/PGA Functional Block Diagram  
1. CDS (Correlated Double Sampling) Circuit  
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The  
black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the  
CDSAMP.  
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).  
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a  
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK  
period, the above sampling and bias operation are paused.  
2. PGA Circuit  
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain  
using 8 bits of register.  
The equation below shows how the gain changes when register value N is from 0 to 255.  
In CDSIN mode: Gain = (–2.36 dB + 0.132 dB) × N (LOG linear).  
In ADCIN mode: Gain = (0.57 times + 0.001784 times) × N (linear).  
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.  
Rev.1.0, Jul 06, 2004, page 6 of 28  
1...3456789...29

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