HD49338HNP

更新时间： 2024-01-19 03:10:59

品牌	Logo	应用领域
瑞萨 - RENESAS		转换器模数转换器
页数	文件大小	规格书
23页	259K
描述
CDS/PGA & 12-bit A/D Converter

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技术参数
数据手册

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HD49338HNP 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	QFP-48	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.6
Is Samacsys：	N	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-XQCC-N48	长度：	7 mm
模拟输入通道数量：	1	位数：	12
功能数量：	1	端子数量：	48
最高工作温度：	75 °C	最低工作温度：	-10 °C
输出位码：	BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	UNSPECIFIED	封装代码：	VQCCN
封装等效代码：	LCC48,.27SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, VERY THIN PROFILE	电源：	3 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	0.8 mm	子类别：	Analog to Digital Converters
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL EXTENDED
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	7 mm
Base Number Matches：	1

HD49338HNP 数据手册

HD49338NP/HNP

3. Automatic Offset Calibration Function and Black-Level Clamp Data Setting

The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.

The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (56

LSB to 304 LSB) set by register are added and input to the DAC.

The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and

terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Compensation Feedback Function

Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets

(including the CCD offset and the CDSAMP offset) are compensated for.

The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged

by the current DAC (see figure 1).

The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is

the one cycle of the OBP.

∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)

Example:When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop

gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8

times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain

(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.

The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be

selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 64 LSB, the high-speed lead-in operation continues,

and when the offset error is 64 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4

H, or 8 H depending on the register settings. See table 2.

Table 1 Loop Gain Multiplication Factor during

High-Speed Lead-In Operation

Table 2 High-Speed Lead-In Operation

Cancellation Time

HGain-Nsel

HGstop-Hsel

(register settings)

Multiplication

Cancellation

Time

[0]

[1]

[0]

[1]

Factor N

1 H

2 H

4 H

8 H

5. Pre-Blanking Function

During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The

ADC digital output is fixed to clamp data (56 to 304 LSB).

Rev.2.00 May 20, 2005 page 7 of 22

1...4 5 678 9 10...23

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与HD49338HNP相关器件

型号	品牌	描述	获取价格	数据表
HD49338NP	RENESAS	CDS/PGA & 12-bit A/D Converter	获取价格
HD49340F	RENESAS	CDS/PGA & 10-bit A/D Converter	获取价格
HD49340F-E	RENESAS	1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48, QFP-48	获取价格
HD49340HF	RENESAS	CDS/PGA & 10-bit A/D Converter	获取价格
HD49340HNP	RENESAS	CDS/PGA & 10-bit A/D Converter	获取价格
HD49340HNP-E	RENESAS	暂无描述	获取价格

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