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HD49338HNP PDF预览

HD49338HNP

更新时间： 2024-02-13 23:54:42
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器模数转换器
页数 文件大小 规格书
23页 259K
描述
CDS/PGA & 12-bit A/D Converter

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HD49338HNP 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：QFP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.6
Is Samacsys：N转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-XQCC-N48长度：7 mm
模拟输入通道数量：1位数：12
功能数量：1端子数量：48
最高工作温度：75 °C最低工作温度：-10 °C
输出位码：BINARY输出格式：PARALLEL, WORD
封装主体材料：UNSPECIFIED封装代码：VQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE电源：3 V
认证状态：Not Qualified采样并保持/跟踪并保持：SAMPLE
座面最大高度：0.8 mm子类别：Analog to Digital Converters
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：7 mm
Base Number Matches：1

HD49338HNP 数据手册

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HD49338NP/HNP  
Internal Functions  
Functional Description  
•
•
•
CDS input  
CCD low-frequency noise is suppressed by CDS (correlated double sampling).  
The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period.  
Gain can be adjusted using 10 bits of register (0.033 dB steps) within the range from –2.36 dB to 31.40 dB. *1  
ADC input  
The center level of the input signal is clamped at 2048 LSB (Typ).  
Gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (–4.86 dB)  
to 5.14 times (14.22 dB). *1  
Y-IN input  
The input signal is clamped at 280 LSB (Typ) by SYNC Tip clamp.  
Automatic offset calibration of PGA and ADC  
DC offset compensation feedback for CCD and CDS  
Pre-blanking  
•
•
•
CDS input operation is protected by separating it from the large input signal.  
Digital output is fixed at 32 LSB.  
•
Digital output enable function  
Note: 1. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.  
Operating Description  
Figure 1 shows CDS/PGA + ADC function block.  
ADCIN  
D0 to D11  
PG  
AMP  
12-bit  
ADC  
CDS  
AMP  
C2  
CDSIN  
Offset  
calibration  
logic  
DAC  
Gain setting  
(register)  
SH  
AMP  
C1  
Clamp data  
(register)  
DC offset  
feedback  
logic  
Current  
DAC  
VRT  
BLKFB  
BLKSH  
BLKC  
C4  
OBP  
C3  
Figure 1 HD49338NP/HNP Functional Block Diagram  
1. CDS (Correlated Double Sampling) Circuit  
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The  
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the  
CDSAMP.  
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The  
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable  
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation  
period. During the PBLK period, the above sampling and bias operation are paused.  
2. PGA Circuit  
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain  
using 10 bits of register.  
The equation below shows how the gain changes when register value N is from 0 to 1023.  
In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) × N (LOG linear).  
In ADCIN mode: Gain = (0.57 times + 0.00446 times) × N (linear).  
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.  
Rev.2.00 May 20, 2005 page 6 of 22  
1...3456789...23

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