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HCS27KMSR PDF预览

HCS27KMSR

更新时间: 2024-11-06 22:40:19
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英特矽尔 - INTERSIL 触发器逻辑集成电路
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8页 183K
描述
Radiation Hardened Triple 3-Input NOR Gate

HCS27KMSR 数据手册

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HCS27MS  
Radiation Hardened  
Triple 3-Input NOR Gate  
September 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T14, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 C1  
12 Y1  
11 C3  
10 B3  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
A2  
B2  
C2  
Y2  
9
8
A3  
Y3  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
GND  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C  
TOP VIEW  
• Input Logic Levels  
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
C1  
Y1  
• Input Current Levels Ii 5µA at VOL, VOH  
A2  
B2  
C3  
B3  
A3  
Y3  
Description  
C2  
The Intersil HCS27MS is a Radiation Hardened Triple 3-Input  
NOR Gate. A Low on all inputs forces the output to a High state.  
Y2  
GND  
8
The HCS27MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
Functional Diagram  
(1, 3, 9)  
An  
The HCS27MS is supplied in a 14 lead Ceramic flatpack (K suffix)  
or a SBDIP Package (D suffix).  
(2, 4, 10)  
Bn  
(12, 6, 8)  
Yn  
Ordering Information  
(13, 5, 11)  
Cn  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
TRUTH TABLE  
INPUTS  
o
o
HCS27DMSR  
HCS27KMSR  
-55 C to +125 C Intersil Class  
S Equivalent  
14 Lead SBDIP  
OUTPUTS  
An  
L
Bn  
L
Cn  
L
Yn  
H
L
o
o
-55 C to +125 C Intersil Class  
S Equivalent  
14 Lead Ceramic  
Flatpack  
L
L
H
L
o
HCS27D/  
Sample  
+25 C  
Sample  
Sample  
Die  
14 Lead SBDIP  
L
H
H
L
L
L
H
L
L
o
HCS27K/  
Sample  
+25 C  
14 Lead Ceramic  
Flatpack  
H
H
H
H
L
L
H
L
L
o
HCS27HMSR  
+25 C  
Die  
H
H
L
H
L
NOTE: L = Logic Level Low, H = Logic level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518766  
File Number 3054.1  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
63  

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