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HCS166K

更新时间： 2024-11-20 23:16:39
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英特矽尔 - INTERSIL 移位寄存器
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9页 229K
描述
Radiation Hardened 8-Bit Parallel-Input/Serial Output Shift Register

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HCS166K 数据手册

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HCS166MS  
Radiation Hardened 8-Bit  
Parallel-Input/Serial Output Shift Register  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/  
Bit-Day (Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD s(Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
VCC  
PE  
DS  
D0  
16  
15  
14  
13  
1
2
3
4
5
6
7
8
D1  
D7  
D2  
Q7  
D3  
12 D6  
D5  
• Fanout (Over Temperature Range)  
- Standard Outputs - 10 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
CE  
11  
10 D4  
MR  
CP  
GND  
9
• Input Logic Levels  
- VIL = 0.3 VCC Max  
- VIH = 0.7 VCC Min  
16 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F16, LEAD FINISH C  
TOP VIEW  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
VCC  
PE  
D7  
DS  
D0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Description  
The Intersil HCS166MS is an 8-bit shift register that has fully  
synchronous serial or parallel data entry selected by an  
active LOW Parallel Enable (PE) input. When the PE is LOW  
one setup time before the LOW-to-HIGH clock transition,  
parallel data is entered into the register. When PE is HIGH,  
data is entered into internal bit position Q0 from Serial Data  
Input (DS), and the remaining bits are shifted one place to  
the right (Q0 → Q1 → Q2m etc.) with each positive-going  
clock transition. For expansion of the register in parallel to  
serial converters, the Q7 output is connected to the DS input  
of the succeeding stage.  
D1  
Q7  
D6  
D2  
D3  
D5  
CE  
D4  
CP  
MR  
GND  
Ordering Information  
The clock input is a gated OR structure which allows one  
input to be used as an active LOW Clock Enable (CE) input.  
The pin assignment for the CP and CE inputs is arbitrary and  
con be reversed for layout convenience. The LOW-to-HIGH  
transition of CE input should only take place while the CP is  
HIGH for predictable operation.  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
o
o
HCS166DMSR -55 C to +125 C Intersil Class S 16 Lead  
Equivalent SBDIP  
o
o
HCS166KMSR -55 C to +125 C Intersil Class S 16 Lead  
Equivalent  
Ceramic  
Flatpack  
A LOW on the Master Reset (MR) input overrides all other  
inputs and clears the register asynchronously, forcing all bit  
positions to a LOW state.  
o
HCS166D/  
Sample  
+25 C  
Sample  
16 Lead  
SBDIP  
The HCS166MS utilizes advanced CMOS/SOS technology  
to achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
o
HCS166K/  
Sample  
+25 C  
Sample  
16 Lead  
Ceramic  
Flatpack  
The HCS166MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
o
HCS166HMSR  
+25 C  
Die  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518758  
File Number 2482.2  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
250  
1234567...9

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