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HCS190DMSR

更新时间： 2024-11-24 23:16:39
品牌 Logo 应用领域
英特矽尔 - INTERSIL 计数器
页数 文件大小 规格书
9页 124K
描述
Radiation Hardened Synchronous 4-Bit Up/Down Counter

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HCS190DMSR 数据手册

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HCS190MS  
Radiation Hardened Synchronous  
4-Bit Up/Down Counter  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• Input Logic Levels  
VCC  
P0  
P1  
Q1  
16  
15  
14  
13  
1
2
3
4
5
6
7
8
Q0  
CP  
CE  
RC  
U/D  
Q2  
12 TC  
PL  
11  
10 P2  
P3  
Q3  
GND  
9
- VIL = 30% of VCC Max  
- VIH = 70% of VCC Min  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
16 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F16  
TOP VIEW  
Description  
The Intersil HCS190MS is an asynchronously presettable BCD  
Decade synchronous counter. Presetting the counter to the  
number on the preset data inputs (P0 - P3) is accomplished by a  
low on the parallel load input (PL). Counting occurs when (PL) is  
high, Count Enable (CE) is low and the Up/Down (U/D) input is  
either low for up-counting or high for down-counting. The counter  
is incremented or decremented synchronously with the low-to-high  
transition of the clock.  
VCC  
P0  
P1  
Q1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q0  
CP  
RC  
TC  
PL  
CE  
U/D  
Q2  
P2  
Q3  
When an overflow or underflow of the counter occurs, the Terminal  
Count output (TC), which is low during counting, goes high and  
remains high for one clock cycle. This output can be used for look-  
ahead carry in high speed cascading. The TC output also initiates  
the Ripple Clock output (RC) which, normally high, goes low and  
remains low for the low-level portion of the clock pulse. These  
counter can be cascaded using the Ripple Carry output.  
P3  
GND  
TRUTH TABLE  
INPUTS  
OUTPUT  
FUNCTION  
PL  
CE  
U/D  
L
CP  
If the decade counter is preset to an illegal state or assumes an  
illegal state when power is applied, it will return to the normal  
sequence in one or two counts.  
H
H
L
L
L
Count Up  
H
Count Down  
Preset  
The HCS190MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
X
H
X
X
X
H
X
No Change  
The HCS190MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
H = High Voltage Level  
L = Low Voltage Level  
X = Immaterial  
=Positive Transistion  
Ordering Information  
PART NUMBER  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
16 Lead SBDIP  
o
o
HCS190DMSR  
-55 C to +125 C  
o
o
HCS190KMSR  
-55 C to +125 C  
16 Lead Ceramic Flatpack  
16 Lead SBDIP  
o
HCS190D/Sample  
HCS190K/Sample  
HCS190HMSR  
+25 C  
o
+25 C  
Sample  
16 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518836  
File Number 2251.2  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
260  
1234567...9

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 		Radiation Hardened Synchronous 4-Bit Up/Down Counter
HCS193D/SAMPLE RENESAS

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16, SIDE
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 		Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional,
HCS193DMSR INTERSIL

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 		Radiation Hardened Synchronous 4-Bit Up/Down Counter
HCS193HMSR INTERSIL

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 		Radiation Hardened Synchronous 4-Bit Up/Down Counter

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