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HCS160HMSR

更新时间： 2024-11-24 22:07:31
品牌 Logo 应用领域
英特矽尔 - INTERSIL 计数器
页数 文件大小 规格书
9页 122K
描述
Radiation Hardened BCD Decade Synchronous Counter

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HCS160HMSR 数据手册

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HCS160MS  
Radiation Hardened  
BCD Decade Synchronous Counter  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
• Fanout (Over Temperature Range)  
-Standard Outputs: 10 LSTTL Loads  
-Bus Driver Outputs: 15 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• Input Logic Levels  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16 VCC  
15 TC  
14 Q0  
13 Q1  
12 Q2  
11 Q3  
10 TE  
P1  
P2  
P3  
PE  
9
SPE  
GND  
-VIL = 30% of VCC Max  
-VIH = 70% of VCC Min  
16 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F16, LEAD FINISH C  
TOP VIEW  
• Input Current Levels Ii ≤ 5µA @ VOL, VOH  
Description  
The Intersil HCS160MS is a Radiation Hardened high speed  
presettable BCD decade synchronous counter that features an  
asynchronous reset and look-ahead carry logic. Counting and  
parallel presetting are accomplished synchronously with the low-  
to-high transition of the clock. A low level on the synchronous  
parallel enable input, SPE, disables counting and allows data at  
the preset inputs, P0 - P3, to be loaded into the counter. The  
counter is reset by a low on the master reset input, MR. Two count  
enables, PE and TE are provided for n-bit cascading. TE also  
controls the terminal count output, TC. The terminal count output  
indicates a maximum count for one clock pulse and is used to  
enable the next cascaded stage to count.  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
TC  
Q0  
P1  
Q1  
P2  
Q2  
P3  
Q3  
PE  
TE  
GND  
SPE  
The HCS160MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
The HCS160MS is supplied in a 16 lead Ceramic flatpack (K suffix)  
or a SBDIP Package (D suffix.)  
Ordering Information  
PART NUMBER  
HCS160DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
16 Lead SBDIP  
o
o
HCS160KMSR  
-55 C to +125 C  
16 Lead Ceramic Flatpack  
16 Lead SBDIP  
o
HCS160D/Sample  
HCS160K/Sample  
HCS160HMSR  
+25 C  
o
+25 C  
Sample  
16 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518834  
File Number 2296.2  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
183  
1234567...9

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HCS161DMSR INTERSIL

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HCS161HMSR INTERSIL

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 		Radiation Hardened Synchronous Counter
HCS161K INTERSIL

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