Datasheet > HCS12CFAMILYPP

HCS12CFAMILYPP

更新时间： 2024-02-21 21:28:31

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
16页	512K
描述
HCS12 C-Family Product Proposal

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数据手册

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HCS12CFAMILYPP 数据手册

MC9S12C-FamilyPP

Rev. 3, 12-May-04

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC9S12C-Family

Product Proposal

16-Bit Microcontroller

Based on Motorola’s market-leading flash technology, members of the MC9S12C-Family deliver the

power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive,

general purpose Industrial and Automotive network applications. MC9S12C-Family members are com-

prised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K

bytes of Flash EEPROM or ROM, up to 4K bytes of RAM, an asynchronous serial communications in-

terface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel

8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC) and up to

one CAN 2.0 A, B software compatible module (MSCAN12). The MC9S12C-Family has full 16-bit data

paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be ad-

justed to suit operational requirements. In addition to the I/O ports available in each module, up to 10

dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. The

MC9S12C-Family is available in 48, 52 and 80 pin QFP packages, with the 80 Pin version pin compat-

ible to the HCS12 B and D- Family derivatives.

The C-Family includes ROM versions MC3S12C128/96/64/32/16 of all devices which provide a further

cost reduction path for applications with high volume and stable code.

Features

• 16-bit HCS12 CORE

— HCS12 CPU

— MMC (memory map and interface)

— INT (interrupt control)

— BDM (background debug mode)

— DBG12 (enhanced debug12 module including breakpoints and change-of-flow trace buffer)

— Multiplexed Expansion Bus (available only in 80 pin package version)

• 16-bit HCS12 CPU

— Upward compatible with M68HC11 instruction set

— Interrupt stacking and programmer’s model identical to M68HC11

— Instruction queue

— Enhanced indexed addressing

• Wake-up interrupt inputs

— Up to 10-port bits available for wake up interrupt function

• Memory options

— 16K, 32K, 64K, 96K and 128K Byte Flash EEPROM (erasable in 512-byte sectors) or

— 16K, 32K, 64K, 96K and 128K Byte ROM

— 2K and 4K Byte RAM

• Analog-to-Digital Converters

— One 8-channel module with 10-bit resolution.

— External conversion trigger capability

• Up to one 1M bit per second, CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

This document contains information on a new product. Specifications and information herein are subject to change without notice.

For More Information On This Product,

Go to: www.freescale.com

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与HCS12CFAMILYPP相关器件

型号	品牌	获取价格	描述	数据表
HCS12COREUG	FREESCALE	获取价格	Device User Guide V01.18
HCS-12-D	SAMTEC	获取价格	Interconnection Device, ROHS COMPLIANT
HCS12DBFAMILYPP	ETC	获取价格	HCS12DB Family Product Proposal
HCS12DFAMILYPP	ETC	获取价格	HCS12 D-Family Product Proposal
HCS12H	FREESCALE	获取价格	16-bit Microcontroller
HCS12HFAMILYPP	ETC	获取价格	HCS12 H-Family Product Proposal
HCS12X	FREESCALE	获取价格	MC9S12XEP100 Reference Manual Covers MC9S12XE Family
HCS12XDFAMILYPP	ETC	获取价格	HCS12 XD-Family Product Brief
HCS132D	INTERSIL	获取价格	Radiation Hardened Quad 2-Input NAND Schmitt Trigger
HCS132D/SAMPLE	RENESAS	获取价格	HC/UH SERIES, QUAD 2-INPUT NAND GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

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