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HCPL-XXXX

更新时间： 2024-01-30 04:44:54
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
24页 669K
描述
3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS

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HCPL-XXXX 数据手册

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ISO721M-EP  
www.ti.com ....................................................................................................................................................................................................... SLLS882–JUNE 2008  
3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS  
1
FEATURES  
•
Signaling Rate 0 Mbps to 150 Mbps  
23  
•
Controlled Baseline  
–
–
Low Propagation Delay  
–
–
–
One Assembly Site  
One Test Site  
Low Pulse Skew (Pulse-Width Distortion)  
•
•
•
•
•
Low-Power Sleep Mode  
High Electromagnetic Immunity  
Low Input Current Requirement  
Failsafe Output  
One Fabrication Site  
•
•
Extended Temperature Performance of  
–55°C to 125°C  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
Drop-In Replacement for Most Opto and  
Magnetic Isolators  
•
•
•
Enhanced Product-Change Notification  
APPLICATIONS  
(1)  
•
Industrial Fieldbus  
Qualification Pedigree  
–
–
–
–
Modbus  
Profibus  
4000-V(peak) Isolation  
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)  
IEC 61010-1  
DeviceNet™ Data Buses  
Smart Distributed Systems (SDS™)  
–
50-kV/µs Transient Immunity Typical  
•
•
•
Computer Peripheral Interface  
Servo Control Interface  
Data Acquisition  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDER INFORMATION  
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated  
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in  
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits  
from entering the local ground, and interfering with or damaging sensitive circuitry.  
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation  
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or  
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure  
the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed  
to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
SDS is a trademark of Honeywell.  
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
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