40 ns Propagation Delay,
CMOS Optocoupler
Technical Data
HCPL-7720 HCPL-7721
HCPL-0720 HCPL-0721
Features
• Multiplexed Data
Transmission
• Computer Peripheral
Interface
• Microprocessor System
Interface
Functional Diagram
• +5 V CMOS Compatibility
• 20 ns max. Prop. Delay Skew
• High Speed: 25 MBd
• 40 ns max. Prop. Delay
**V
DD1
1
2
8
7
V
**
DD2
V
NC*
I
• 10 kV/µs Minimum Common
Mode Rejection
• –40 to 85°C Temp. Range
• Safety and Regulatory
Approvals
UL Recognized
2500 V rms for 1 min. per
UL 1577 for HCPL-072X,
3750 V rms for 1 min. per
UL 1577 for HCPL-772X
CSA Component Acceptance
Notice #5
I
O
Description
3
4
6
5
*
V
O
Available in either an 8-pin DIP or
SO-8 package style respectively,
the HCPL-772X or HCPL-072X
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with
very low power consumption. The
HCPL-772X/072X require only
two bypass capacitors for
LED1
GND
GND
1
2
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
V , INPUT
I
LED1
V
, OUTPUT
O
H
L
OFF
ON
H
L
complete CMOS compatability.
VDE 0884
– VIORM = 630 Vpeak for
HCPL-772X Option 060
– VIORM = 560 Vpeak for
HCPL-072X Option 060
Basic building blocks of the
HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED
and a CMOS detector IC. A CMOS
logic input signal controls the
LED driver IC which supplies
current to the LED. The detector
IC incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Applications
• Digital Fieldbus Isolation:
CC-Link, DeviceNet,
Profibus, SDS
• AC Plasma Display Panel
Level Shifting
*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION:Itisadvisedthatnormalstaticprecautionsbetakeninhandlingandassemblyofthiscomponent
to prevent damage and/or degradation which may be induced by ESD.