Datasheet > HCPL-0452-060

HCPL-0452-060

更新时间： 2024-11-10 22:28:43

品牌	Logo	应用领域
安捷伦 - AGILENT		光电输出元件
页数	文件大小	规格书
16页	150K
描述
Single Channel, High Speed Optocouplers

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中文翻译

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数据手册

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HCPL-0452-060 数据手册

Single Channel, High Speed

Optocouplers

6N135/6

Technical Data

HCNW135/6

HCNW4502/3

HCPL-2502

HCPL-0452/3

HCPL-0500/1

HCPL-4502/3

Features

Description

Applications

• High Voltage Insulation

• Video Signal Isolation

• Power Transistor Isolation

in Motor Drives

• Line Receivers

• Feedback Element in

Switched Mode Power

Supplies

• High Speed Logic Ground

Isolation – TTL/TTL, TTL/

CMOS, TTL/LSTTL

• Replaces Pulse Transformers

• Replaces Slow

Phototransistor Isolators

• Analog Signal Ground

Isolation

These diode-transistor optocoup-

lers use an insulating layer

between a LED and an integrated

photodetector to provide elec-

trical insulation between input

and output. Separate connections

for the photodiode bias and

output-transistor collector

increase the speed up to a

hundred times that of a conven-

tional phototransistor coupler by

reducing the base-collector

capacitance.

• 15 kV/µs Minimum Common

Mode Transient Immunity at

V_CM= 1500 V (4503/0453)

• High Speed: 1 Mb/s

• TTL Compatible

• Available in 8-Pin DIP, SO-8,

Widebody Packages

• Open Collector Output

• Guaranteed Performance

from Temperature: 0°C

to 70°C

• Safety Approval

UL Recognized – 3750 V rms

for 1 minute (5000 V rms for

1 minute for HCNW and

Option 020 devices) per

UL1577

CSA Approved

IEC/EN/DIN EN 60747-5-2

Approved

Functional Diagram

–V_IORM= 630 V peak for

HCPL-4503#060

–V_IORM= 1414 V peak for

HCNW devices

ANODE

CATHODE

TRUTH TABLE

(POSITIVE LOGIC)

LED

OFF

LOW

HIGH

• Dual Channel Version

Available (253X/4534/053X/

0534)

GND

• MIL-PRF-38534 Hermetic

Version Available (55XX/

65XX/4N55)

* NOTE: FOR 4502/3, 0452/3,

PIN 7 IS NOT CONNECTED.

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation which may be induced by ESD.

12 3 4 5 6 7...16

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