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HCF4013BF PDF预览

HCF4013BF

更新时间: 2024-11-03 22:56:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
12页 289K
描述
NAND GATES

HCF4013BF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:FRIT SEALED, CERAMIC, DIP-14
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.81
其他特性:LG_MAX系列:4000/14000/40000
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:20 mm逻辑集成电路类型:D FLIP-FLOP
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):300 ns座面最大高度:5 mm
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:12 MHzBase Number Matches:1

HCF4013BF 数据手册

 浏览型号HCF4013BF的Datasheet PDF文件第2页浏览型号HCF4013BF的Datasheet PDF文件第3页浏览型号HCF4013BF的Datasheet PDF文件第4页浏览型号HCF4013BF的Datasheet PDF文件第5页浏览型号HCF4013BF的Datasheet PDF文件第6页浏览型号HCF4013BF的Datasheet PDF文件第7页 
HCC4011B/12B/23B  
HCF4011B/12B/23B  
NAND GATES  
QUAD 2 INPUT HCC/HCF 4011B  
DUAL 4 INPUT HCC/HCF 4012B  
TRIPLE 3 INPUT HCC/HCF 4023B  
.
PROPAGATION DELAY TIME = 60ns (typ.) AT  
CL = 50pF, VDD = 10V  
BUFFERED INPUTS AND OUTPUTS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
.
.
EY  
F
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
.
.
.
100% TESTED FOR QUIESCENT CURRENT  
5V, 10V AND 15V PARAMETRIC RATINGS  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD No. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC40XXBF  
HCF40XXBM1  
HCF40XXBEY  
HCF40XXBC1  
DESCRIPTION  
The HCC4011B, HCC4012B and HCC4023B (ex-  
tended temperature range) and HCF4011B,  
HCF4012B and HCF4023B (intermediate tempera-  
ture range) are monolithic, integrated circuit, avail-  
able in 14-lead dual in-line plastic or ceramic  
package and plastic micropackage.  
The HCC/HCF4011B, HCC/HCF4012B and  
HCC/HCF4023B NAND gates provide the system  
designer with direct implementation of the NAND  
function and supplement the existing family of  
COS/MOS gates. All inputs and outputs are buf-  
fered.  
PIN CONNECTIONS  
4011B  
4012B  
4023B  
June 1989  
1/12  

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