Datasheet > H5TQ4G83EFR-RDI

H5TQ4G83EFR-RDI

更新时间： 2023-12-06 20:02:09

品牌	Logo	应用领域
海力士 - HYNIX		双倍数据速率
页数	文件大小	规格书
33页	1429K
描述
DDR3

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中文翻译

获取价格

数据手册

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H5TQ4G83EFR-RDI 数据手册

Description

The H5TQ4G83EFR-xxC,H5TQ4G63EFR-xxC, H5TQ4G83EFR-xxI, H5TQ4G63EFR-xxI, H5TQ4G83EFR-xxL,

H5TQ4G63EFR-xxL, H5TQ4G83EFR-xxJ, H5TQ4G63EFR-xxJ, H5TQ4G83EFR-xxK and H5TQ4G63EFR-xxK

are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main

memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3

SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While

all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data

paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Device Features and Ordering Information

FEATURES

• AverageRefreshCycle (Tcaseof0^oC~105^oC)

- 7.8 µs at 0^oC ~ 85 ^oC

•

VDD=VDDQ=1.5V +/- 0.075V

Fully differential clock inputs (CK, CK) operation

Differential Data Strobe (DQS, DQS)

- 3.9 µs at 85^oC ~ 95 ^oC

- 1.95 µs at 95^oC ~ 105 ^oC

On chip DLL align DQ, DQS and DQS transition with CK

transition

Commercial Temperature( 0^oC ~ 95 ^oC)

Industrial Temperature( -40^oC ~ 95 ^oC)

Automotive Temperature( -40^oC ~ 105 ^oC)

•

DM masks write data-in at the both rising and falling

edges of the data strobe

All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

•

JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)

Driver strength selected by EMRS

Dynamic On Die Termination supported

Asynchronous RESET pin supported

ZQ calibration supported

•

Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13

and 14 supported

Programmable additive latency 0, CL-1, and CL-2

supported

TDQS (Termination Data Strobe) supported (x8 only)

Write Levelization supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9

and 10

8 bit pre-fetch

Programmable burst length 4/8 with both nibble

sequential and interleave mode

•

BL switch on the fly

8banks

* This product in compliance with the RoHS directive.

Rev. 1.4/ Oct. 2020

1 234 5 6 7...33

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