Datasheet > H0700KC17F

H0700KC17F

更新时间： 2024-02-20 05:03:13

品牌	Logo	应用领域
IXYS		栅栅极
页数	文件大小	规格书
15页	319K
描述
Symmetrical GTO SCR, 700A I(T)RMS, 1700V V(DRM), 1190V V(RRM), 1 Element

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技术参数
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H0700KC17F 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	DISK BUTTON, O-CXDB-X4
Reach Compliance Code：	unknown	HTS代码：	8541.30.00.80
风险等级：	5.8	配置：	SINGLE
最大直流栅极触发电流：	1500 mA	JESD-30 代码：	O-CXDB-X4
元件数量：	1	端子数量：	4
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装形状：	ROUND
封装形式：	DISK BUTTON	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	最大均方根通态电流：	700 A
断态重复峰值电压：	1700 V	重复峰值反向电压：	1190 V
表面贴装：	YES	端子形式：	UNSPECIFIED
端子位置：	UNSPECIFIED	处于峰值回流温度下的最长时间：	NOT SPECIFIED
触发设备类型：	SYMMETRICAL GTO SCR	Base Number Matches：	1

H0700KC17F 数据手册

WESTCODE An IXYS Company

Fast Symmetrical Gate Turn-Off Thyristor type H0700KC17#

2 Characteristics

2.1 Instantaneous on-state voltage

Measured using a 500µs square pulse, see also the curves of figure 2 for other values of I_TM.

2.2 Latching and holding current

These are considered to be approximately equal and only the latching current is measured, type test only

as outlined below. The test circuit and wave diagrams are given in diagram 4. The anode current is

monitored on an oscilloscope while V_Dis increased, until the current is seen to flow during the un-gated

period between the end of I_Gand the application of reverse gate voltage. Test frequency is 100Hz with I_GM

& I_Gas for t_dof characteristic data.

I_G

100µs

I_GM

Gate current

16V

100µs

Anode current

unlatched condition

Unlatched

Latched

Anode current

Latched condition

DUT

Gate-drive

Diagram 4, Latching test circuit and waveforms.

2.3 Critical dv/dt

The gate conditions are the same as for 1.1, this characteristic is for off-state only and does not relate to

dv/dt at turn-off. The measurement, type test only, is conducted using the exponential ramp method as

shown in diagram 5. It should be noted that GTO thyristors have a poor static dv/dt capability if the gate is

open circuit or R_GKis high impedance. Typical values: - dv/dt<30V/µs for R_GK>10Ω.

Diagram 5, Definition of dV/dt.

2.4 Off-state leakage.

For I_DRM& I_RRMsee notes 1.1 & 1.2 for gate leakage I_GK, the off-state gate circuit is required to sink this

leakage and still maintain minimum of –2 Volts. See diagram 6.

Diagram 6.

Data Sheet. Type H0700KC17# Issue 1

Page 5 of 15

April, 2004

1 2 3 456 7 8...15

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