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GVT81256K36T-12 PDF预览

GVT81256K36T-12

更新时间: 2024-11-23 20:02:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 64K
描述
Multi-Port SRAM, 256KX36, 6ns, CMOS, PQFP176, TQFP-176

GVT81256K36T-12 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:TQFP-176
Reach Compliance Code:compliant风险等级:5.92
最长访问时间:6 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G176JESD-609代码:e0
长度:24 mm内存密度:9437184 bit
内存集成电路类型:MULTI-PORT SRAM内存宽度:36
功能数量:1端口数量:2
端子数量:176字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP176,1.0SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.1 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24 mm
Base Number Matches:1

GVT81256K36T-12 数据手册

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ADVANCE INFORMATION  
GVT81256K36/GVT81128K36  
256K/128K X 36 DUAL PORT SRAM  
GALVANTECH, INC.  
DUAL PORT  
SYNCHRONOUS  
SRAM  
256K/128K X 36 SRAM  
+3.3V SUPPLY, FULLY REGISTERED  
TWO BI-DIRECTIONAL DATA BUSES  
FEATURES  
GENERAL DESCRIPTION  
Fast clock speed: 100, and 83 MHz  
Fast Access Times: 5.0/6.0 ns Max  
Fully independent clock per port  
Single 3.3V -5% and +5% power supply VCC  
Separate VCCQ for output buffer  
Two chip enables for simple depth expansion  
Address, Data Input, CE1X#, CE2X, CE1Y#, CE2Y,  
WEX#, WEY#, and Data Output Registers On-Chip  
Concurrent Reads and Writes  
The GVT81256K36/GVT81128K36 SRAM integrates  
262,144x36/131,072x36 SRAM cells with advanced  
synchronous peripheral circuitry. It employs high-speed, low  
power CMOS designs using advanced triple-layer polysilicon,  
double-layer metal technology. Each memory cell consists of  
four transistors and two high valued resistors.  
The GVT81256K36/GVT81128K36 allows the user to  
concurrently perform reads or writes cycles on the two data  
ports. The two address ports (AX, AY) determine the read or  
write locations for their respective data ports (DQX, DQY).  
All input pins of each port, except output enable pins  
(OEX#, OEY#), are gated by registers controlled by the  
respective positive-edge-triggered clock inputs CLKX or  
CLKY. The synchronous inputs of Port X include all  
addresses (AX), all data inputs (DQX), depth-expansion chip  
enables (CE1X# and CE2X), and read-write control (WEX#).  
The synchronous inputs of Port Y include all addresses (AY),  
all data inputs (DQY), depth-expansion chip enables (CE1Y#  
and CE2Y), and read-write control (WEY#).  
Two Bi-Directional Data Buses  
Can be Configured as Separate I/O  
Asynchronous Output Enables (OEX#, OEY#)  
LVTTL Compatible I/O  
Self-Timed Write  
Automatic power down  
176-Pin TQFP Package  
OPTIONS  
MARKING  
Timing  
For the case when AX and AY are the same, certain  
protocols are followed. If the rising edges of the two clocks  
5.0ns access/10.0 cycle  
6.0ns access/12.0 cycle  
-10  
-12  
are separated by at least t , the transaction associated with  
CO  
the earlier clock edge is guaranteed to be performed first.  
Otherwise, the transactions may occur in any order.  
Packages  
176-pin TQFP  
T
The GVT81256K36/GVT81128K36 operate from  
a
+3.3V power supply. All inputs and outputs are LVTTL  
compatible. These dual I/O, dual address synchronous  
SRAMs are well suited for ATM, Ethernet switches, routers,  
cell/frame buffers, SNA switches and shared memory  
applications.  
Galvantech, Inc. reserves the right to chang e  
products or specifications without notice.  
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051  
Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com  
Rev. 12/99  

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