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GVT81256P36T-10 PDF预览

GVT81256P36T-10

更新时间: 2024-11-19 21:13:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
14页 60K
描述
Standard SRAM, 256KX36, 5ns, CMOS, PQFP176, TQFP-176

GVT81256P36T-10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-176
针数:176Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:5 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G176
JESD-609代码:e0长度:24 mm
内存密度:9437184 bit内存集成电路类型:STANDARD SRAM
内存宽度:36功能数量:1
端口数量:2端子数量:176
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP176,1.0SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.1 A
最小待机电流:3.13 V子类别:SRAMs
最大压摆率:0.35 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24 mmBase Number Matches:1

GVT81256P36T-10 数据手册

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ADVANCE INFORMATION  
GVT81256P36/GVT81128P36  
256K/128K X 36 PIPELINED SRAM  
GALVANTECH, INC.  
DUAL I/O  
DUAL ADDRESS  
SYNCHRONOUS SRAM  
256K/128K X 36 SRAM  
+3.3V SUPPLY, FULLY REGISTERED  
TWO BI-DIRECTIONAL DATA BUSES  
FEATURES  
GENERAL DESCRIPTION  
Fast clock speed: 133, 100, and 83 MHz  
Fast Access Times: 4.0/5.0/6.0 ns Max  
Single Clock Operation  
Single 3.3V -5% and +5% power supply VCC  
Separate VCCQ for output buffer  
Two chip enables for simple depth expansion  
Address, Data Input, CE1X#, CE2X, CE1Y#, CE2Y,  
PTX#, PTY#, WEX#, WEY#, and Data Output Registers  
On-Chip  
The GVT81256P36/GVT81128P36 SRAM integrates  
262,144x36/131,072x36 SRAM cells with advanced  
synchronous peripheral circuitry. It employs high-speed, low  
power CMOS designs using advanced triple-layer polysilicon,  
double-layer metal technology. Each memory cell consists of  
four transistors and two high valued resistors.  
The GVT81256P36/GVT81128P36 allows the user to  
concurrently perform reads, writes, or pass-through cycles in  
combination on the two data ports. The two address ports  
(AX, AY) determine the read or write locations for their  
respective data ports (DQX, DQY).  
All input pins except output enable pins (OEX#, OEY#)  
are gated by registers controlled by a positive-edge-triggered  
clock input (CLK). The synchronous inputs include all  
addresses, all data inputs, depth-expansion chip enables  
(CE1X#, CE2X, CE1Y# and CE2Y), pass-through controls  
(PTX# and PTY#), and read-write control (WEX# and  
WEY#).  
Concurrent Reads and Writes  
Two Bi-Directional Data Buses  
Can be Configured as Separate I/O  
Pass-Through Feature  
Asynchronous Output Enables (OEX#, OEY#)  
LVTTL Compatible I/O  
Self-Timed Write  
Automatic power down  
176-Pin TQFP Package  
The pass-through feature allows data to be passed from  
one port to the other, in either direction. The PTX# input must  
be asserted to pass data from port X to port Y. The PTY# will  
likewise pass data from port Y to port X. A pass-through  
operation takes precedence over a read operation.  
For the case when AX and AY are the same, certain  
protocols are followed. If both ports are read, the reads occur  
normally. If one port is written and the other is read, the read  
from the array will occur before the data is written. If both  
ports are written, only the data on DQY will be written to the  
array.  
OPTIONS  
MARKING  
Timing  
4.0ns access/7.5ns cycle  
5.0ns access/10.0 cycle  
6.0ns access/12.0 cycle  
-7.5  
-10  
-12  
Packages  
176-pin TQFP  
T
The GVT81256P36/GVT81128P36 operate from a +3.3V  
power supply. All inputs and outputs are LVTTL compatible.  
These dual I/O, dual address synchronous SRAMs are well  
suited for ATM, Ethernet switches, routers, cell/frame buffers,  
SNA switches and shared memory applications.  
Galvantech, Inc. reserves the right to chang e  
products or specifications without notice.  
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051  
Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com  
Rev. 12/99  

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