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GS9020-CFV PDF预览

GS9020-CFV

更新时间: 2024-01-27 02:26:36
品牌 Logo 应用领域
其他 - ETC 商用集成电路
页数 文件大小 规格书
30页 271K
描述
Serial Digital Video Input Processor

GS9020-CFV 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:,针数:80
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G80
端子数量:80封装主体材料:PLASTIC/EPOXY
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

GS9020-CFV 数据手册

 浏览型号GS9020-CFV的Datasheet PDF文件第2页浏览型号GS9020-CFV的Datasheet PDF文件第3页浏览型号GS9020-CFV的Datasheet PDF文件第4页浏览型号GS9020-CFV的Datasheet PDF文件第5页浏览型号GS9020-CFV的Datasheet PDF文件第6页浏览型号GS9020-CFV的Datasheet PDF文件第7页 
GENLINX II GS9020  
Serial Digital Video Input Processor  
DATA SHEET  
FEATURES  
DESCRIPTION  
The GS9020 is specifically designed to deserialize SMPTE  
259M serial digital signals. The inclusion of Error Detection  
and Handling (EDH) ensures the integrity of the data being  
received from the serial digital interface (SDI). Internal 75  
termination resistors allow INTERLINX™ seamless  
connection with the GS9035 Reclocker or the GS9025  
Receiver, thus providing a complete, high performance,  
digital video input processor with EDH, digital sync signal  
generation, and other system features.  
• fully compatible with SMPTE 259M  
• auto-standard operation to 540MHz  
• embedded EDH and data processing core  
• selectable loop through or re-serialized EDH-  
processed serial output  
• noise immune HVF timing signal outputs  
• configurable FIFO reset pulse for clearing  
downstream FIFOs  
• ANC header and TRS-ID correction for all standards  
• user controlled output blanking  
• ITU-R-601 output clipping for active picture area  
• ancillary data indication  
The GS9020 also includes a parallel to serial converter and  
NRZI scrambler to provide re-serialized, EDH compliant  
data output. The EDH core implements EDH insertion and  
extraction according to SMPTE RP-165. This core also  
generates noise immune timing signals such as horizontal  
sync, vertical blanking, field ID and ancillary data  
identification. It also provides many system features such  
as a FIFO reset pulse (which can be programmed to  
coincide with either EAV or SAV), TRS-ID and ANC header  
correction, user controlled output blanking and ITU-R-601  
output clipping. The GS9020 has an I²C (Inter-Integrated  
Circuit, I²C is a registered Trademark of Philips) serial  
interface bus and an 8-bit parallel port for external access  
to all error flags and device configuration bits.  
• low system power  
• selectable I²C interface or 8-bit parallel port for access  
to EDH flags and device configuration bits  
• EDH flags also available on dedicated pins  
• seamless flag mapping to GS9021 EDH coprocessor  
• 80 pin LQFP  
APPLICATIONS  
SMPTE 259M serial digital receiver for composite and  
component standards including 4:4:4:4 at 540Mb/s with  
EDH processing; Noise immune digital sync and timing  
generation; Cost effective EDH insertion and checking for  
serial routing and distribution applications.  
ORDERING INFORMATION  
PART NUMBER  
GS9020-CFV  
GS9020-CTV  
PACKAGE  
TEMPERATURE  
0°C to 70°C  
80 pin LQFP Tray  
80 pin LQFP Tape  
0°C to 70°C  
SDOMODE  
PARALLEL TO  
SDO  
SERIAL  
CONVERTER  
WITH SCRAMBLER  
0
1
BUF  
SDO  
10  
FRAMED  
DATA [9:0]  
DESCRAMBLER  
DOUT[9:0]  
FIFO_RESET  
HVF  
SDI  
SDI  
10  
SERIAL TO  
PARALLEL  
CONVERTER  
BUF  
SYNC  
DETECTOR  
5
4
EDH  
CLIP_TRS  
AND DATA  
PROCESSING  
CORE  
SCI  
SCI  
ANC_CHKSM  
PCLK OUT  
RESET  
ALIGNING  
CONTROL  
UNIT  
BUF  
PRESCALER  
STANDARDS  
INDICATOR  
HOSTIF  
TRS_ERR  
7
DEDICATED  
FLAG PORT  
PCLKOUT  
BLOCK DIAGRAM  
Revision Date: November 1999  
Document No. 521 - 66 - 05  
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3  
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com  
www.gennum.com  

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