Datasheet > GS88237BB-200VT

GS88237BB-200VT

更新时间： 2024-11-11 20:37:15

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
28页	1528K
描述
Cache SRAM, 256KX36, 2.5ns, CMOS, PBGA119, FPBGA-119

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技术参数
数据手册

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GS88237BB-200VT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	119	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.74	最长访问时间：	2.5 ns
其他特性：	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	9437184 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	119	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.99 mm	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS88237BB-200VT 数据手册

GS88237BB/D-xxxV

250 MHz–200 MHz

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

256K x 36

9Mb SCD/DCD Sync Burst SRAM

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V or 2.5 V core power supply

SCD and DCD Pipelined Reads

The GS88237BB/D-xxxV is a SCD (Single Cycle Deselect) and

• 1.8 V or 2.5 V I/O supply

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-bump and 165-bump BGA packages

• RoHS-compliant 119-bump and 165-bump BGA packages

available

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

Functional Description

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Applications

The GS88237BB/D-xxxV is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS88237BB/D-xxxV operates on a 1.8 V or 2.5 V power

supply. All inputs are 1.8 V or 2.5 V compatible. Separate output

power (V_DDQ) pins are used to decouple output noise from the

internal circuits and are 1.8 V or 2.5 V compatible.

Parameter Synopsis

-250 -200 Unit

2.5

4.0

2.5

5.0

Pipeline

3-1-1-1

tCycle

Curr (x36)

330

270

Rev: 1.06 12/2008

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

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与GS88237BB-200VT相关器件

型号	品牌	获取价格	描述	数据表
GS88237BB-250	GSI	获取价格	256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BB-250I	GSI	获取价格	256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BB-250IV	GSI	获取价格	256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BB-250IVT	GSI	获取价格	Cache SRAM, 256KX36, 2.5ns, CMOS, PBGA119, FPBGA-119
GS88237BB-250T	GSI	获取价格	Cache SRAM, 256KX36, 2.3ns, CMOS, PBGA119, FPBGA-119
GS88237BB-250V	GSI	获取价格	256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BB-275IT	GSI	获取价格	Cache SRAM, 256KX36, 2.3ns, CMOS, PBGA119, PLASTIC, BGA-119
GS88237BB-300	GSI	获取价格	256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BB-300I	GSI	获取价格	256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BB-300IT	GSI	获取价格	Cache SRAM, 256KX36, 2.2ns, CMOS, PBGA119, FPBGA-119

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