Datasheet > 存储 > SRAM> GS88132BD-150IV

GS88132BD-150IV

更新时间： 2024-11-25 02:56:31

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
36页	1529K
描述
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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技术参数
数据手册

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GS88132BD-150IV 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA,
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.72	最长访问时间：	7.5 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	8388608 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	32	功能数量：	1
端子数量：	165	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

GS88132BD-150IV 数据手册

GS88118/32/36B(T/D)-xxxV

250 MHz–150 MHz

100-pin TQFP & 165-bump BGA

Commercial Temp

512K x 18, 256K x 32, 256K x 36

1.8 V or 2.5 V V

9Mb Sync Burst SRAMs

1.8 V or 2.5 V I/O

Industrial Temp

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Features

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

packages

• RoHS-compliant 100-lead TQFP and 165-bump BGA

packages available

SCD Pipelined Reads

The GS88118/32/36B(T/D)-xxxV is a SCD (Single Cycle

Deselect) pipelined synchronous SRAM. DCD (Dual Cycle

Deselect) versions are also available. SCD SRAMs pipeline

deselect commands one stage less than read commands. SCD

RAMs begin turning off their outputs immediately after the

deselect command has been captured in the input registers.

Byte Write and Global Write

Functional Description

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS88118/32/36B(T/D)-xxxV is a 9,437,184-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Core and Interface Voltages

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

The GS88118/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5 V

power supply. All input are 1.8 V and 2.5 V compatible.

Separate output power (V

) pins are used to decouple

DDQ

output noise from the internal circuits and are 1.8 V and 2.5 V

compatible.

Paramter Synopsis

-250

-200

-150

Unit

t_KQ

3.0

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

200

230

170

195

140

160

t_KQ

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

160

185

140

160

128

145

Rev: 1.00 6/2006

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...36

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与GS88132BD-150IV相关器件

型号	品牌	获取价格	描述	数据表
GS88132BD-150IVT	GSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS88132BD-150T	GSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS88132BD-150V	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BD-150VT	GSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS88132BD-200	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BD-200I	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BD-200IT	GSI	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS88132BD-200IV	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88132BD-200IVT	GSI	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS88132BD-200T	GSI	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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