Datasheet > GS880E18BGT-166I

GS880E18BGT-166I

更新时间： 2024-11-11 05:56:11

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
24页	681K
描述
Cache SRAM, 512KX18, 7ns, CMOS, PQFP100, TQFP-100

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GS880E18BGT-166I 数据手册

GS880E18/32/36BT-250/225/200/166/150/133

100-Pin TQFP

Commercial Temp

Industrial Temp

250 MHz–133 MHz

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

2.5 V or 3.3 V V_DD

2.5 V or 3.3 V I/O

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Dual Cycle Deselect (DCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode pin

low places the RAM in Flow Through mode, causing output

data to bypass the Data Output Register. Holding FT high

places the RAM in Pipeline mode, activating the rising-edge-

triggered Data Output Register.

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

-250 -225 -200 -166 -150 -133 Unit

DCD Pipelined Reads

Pipeline

3-1-1-1

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

The GS880E18/32/36BT is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

tCycle

Curr (x18) 280 255 230 200 185 165 mA

Curr (x32/x36) 330 300 270 230 215 190 mA

3.3 V

2.5 V

Curr (x18) 275 250 230 195 180 165 mA

Curr (x32/x36) 320 295 265 225 210 185 mA

Flow

Through

2-1-1-1

5.5 6.0 6.5 7.0 7.5 8.5 ns

tCycle

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Curr (x18) 175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

3.3 V

2.5 V

Curr (x18) 175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

Sleep Mode

Functional Description

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Applications

The GS880E18/32/36BT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Core and Interface Voltages

The GS880E18/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

Rev: 1.00b 12/2002

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS880E18BGT-166I相关器件

型号	品牌	获取价格	描述	数据表
GS880E18BGT-166T	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PQFP100, TQFP-100
GS880E18BGT-200	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS880E18BGT-200I	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS880E18BGT-200IT	GSI	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880E18BGT-200IV	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS880E18BGT-200IVT	GSI	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880E18BGT-200T	GSI	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880E18BGT-200V	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS880E18BGT-200VT	GSI	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS880E18BGT-225IT	GSI	获取价格	Cache SRAM, 512KX18, 6ns, CMOS, PQFP100, TQFP-100

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