Datasheet > GS8672T36AGE-300T

GS8672T36AGE-300T

更新时间： 2024-11-24 10:48:27

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
29页	1003K
描述
DDR SRAM, 2MX36, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165

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Preliminary

GS8672T18/36AE-333/300/250/200

333 MHz–200 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II™

Burst of 2 ECCRAM™

1.8 V V

1.8 V and 1.5 V

DDQ

Features

Clocking and Addressing Schemes

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 144Mb

devices

The GS8672T18/36AE SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaDDR-II ECCRAMs always

transfer data in two packets. When a new address is loaded, A0

presets an internal 1-bit address counter. The counter

increments by 1 (toggles) for each beat of a burst of two data

transfer.

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

On-Chip Error Correction Code

SigmaDDR™ Family Overview

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

The GS8672T18/36AE SigmaDDR-II ECCRAMs are built in

compliance with the SigmaDDR-II SRAM pinout standard for

Common I/O synchronous SRAMs. They are 75,497,472-bit

(72Mb) SRAMs. The GS8672T18/36AE SigmaDDR-II

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02 5/2010

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...29

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与GS8672T36AGE-300T相关器件

型号	品牌	获取价格	描述	数据表
GS8672T36AGE-333IT	GSI	获取价格	DDR SRAM, 2MX36, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165
GS8672T36AGE-333T	GSI	获取价格	DDR SRAM, 2MX36, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-165
GS8672T37AE-300T	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T37AE-333	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T37AE-333IT	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T37AE-375	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T37AE-400	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T37AE-400I	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8672T37AGE-300	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T37AGE-300I	GSI	获取价格	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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