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GS8662S18BD-300IT PDF预览

GS8662S18BD-300IT

更新时间： 2024-11-06 19:18:47
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
35页 1285K
描述
Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165

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GS8662S18BD-300IT 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.48
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：75497472 bit内存集成电路类型：STANDARD SRAM
内存宽度：18功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX18封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

GS8662S18BD-300IT 数据手册

 浏览型号GS8662S18BD-300IT的Datasheet PDF文件第2页浏览型号GS8662S18BD-300IT的Datasheet PDF文件第3页浏览型号GS8662S18BD-300IT的Datasheet PDF文件第4页浏览型号GS8662S18BD-300IT的Datasheet PDF文件第5页浏览型号GS8662S18BD-300IT的Datasheet PDF文件第6页浏览型号GS8662S18BD-300IT的Datasheet PDF文件第7页 
GS8662S08/09/18/36BD-400/350/333/300/250  
72Mb SigmaSIOTM DDR -II  
Burst of 2 SRAM  
400 MHz–250 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
Clocking and Addressing Schemes  
• Simultaneous Read and Write SigmaSIO™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• DLL circuitry for wide output data valid window and future  
frequency scaling  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous  
device. It employs dual input register clock inputs, K and K.  
The device also allows the user to manipulate the output  
register clock input quasi independently with dual output  
register clock inputs, C and C. If the C clocks are tied high, the  
K clocks are routed internally to fire the output registers  
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also  
supplies Echo Clock outputs, CQ and CQ, which are  
synchronized with read data output. When used in a source  
synchronous clocking scheme, the Echo Clock outputs can be  
used to fire input registers at the data’s destination.  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ mode pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Each internal read and write operation in a SigmaSIO DDR-II  
B2 RAM is two times wider than the device I/O bus. An input  
data bus de-multiplexer is used to accumulate incoming data  
before it is simultaneously written to the memory array. An  
output data multiplexer is used to capture the data produced  
from a single memory array read and then route it to the  
appropriate output drivers as needed. Therefore, the address  
field of a SigmaSIO DDR-II B2 is always one address pin less  
than the advertised index depth (e.g., the 8M x 8 has an 4M  
addressable index).  
SigmaSIO™ Family Overview  
GS8662S08/09/18/36BD are built in compliance with the  
SigmaSIO DDR-II SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. These are the first in a family of wide, very low  
voltage HSTL I/O SRAMs designed to operate at the speeds  
needed to implement economical high performance  
networking systems.  
Parameter Synopsis  
-400  
2.5 ns  
0.45 ns  
-350  
2.86 ns  
0.45 ns  
-333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
0.45 ns  
-250  
4.0 ns  
0.45 ns  
tKHKH  
tKHQV  
Rev: 1.02c 12/2011  
1/35  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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