Datasheet > GS8662Q07BD-300T

GS8662Q07BD-300T

更新时间： 2024-01-12 09:41:08

品牌	Logo	应用领域
GSI		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
28页	390K
描述
DDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

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GS8662Q07BD-300T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.47
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	67108864 bit
内存集成电路类型：	DDR SRAM	内存宽度：	8
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.255 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.85 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

GS8662Q07BD-300T 数据手册

浏览型号GS8662Q07BD-300T的Datasheet PDF文件第10页

GS8662Q07/10/19/37BD-357/333/300/250/200

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

SigmaQuad-II B2 SRAM DDR Read

The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,

begins a read cycle. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II B2 SRAM DDR Write

The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of

K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is

clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on

the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.

Special Functions

Byte Write and Nybble Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble

Write Enable” and “NWx” may be substituted in all the discussion above.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

BW0

BW1

D0–D8

Data In

D9–D17

Don’t Care

Data In

Beat 1

Beat 2

Don’t Care

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 3

D0–D8

Byte 4

D9–D17

Written

Unchanged

Written

Beat 1

Beat 2

Rev: 1.02b 11/2011

7/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1...4 5 678 9 10...28

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与GS8662Q07BD-300T相关器件

型号	品牌	描述	获取价格	数据表
GS8662Q07BD-333	GSI	JEDEC-standard pinout and package	获取价格
GS8662Q07BD-333I	GSI	JEDEC-standard pinout and package	获取价格
GS8662Q07BD-357	GSI	72Mb SigmaQuad-IITM Burst of 2 SRAM	获取价格
GS8662Q07BD-357I	GSI	DDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165	获取价格
GS8662Q07BD-357IT	GSI	DDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165	获取价格
GS8662Q07BGD-200	GSI	72Mb SigmaQuad-IITM Burst of 2 SRAM	获取价格

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