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GS8640Z36GT-250IV PDF预览

GS8640Z36GT-250IV

更新时间： 2024-11-13 04:56:23
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
22页 969K
描述
72Mb Pipelined and Flow Through Synchronous NBT SRAM

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中文翻译

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GS8640Z36GT-250IV 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41Factory Lead Time：9 weeks
风险等级：5.3最长访问时间：6.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLYJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS8640Z36GT-250IV 数据手册

 浏览型号GS8640Z36GT-250IV的Datasheet PDF文件第2页浏览型号GS8640Z36GT-250IV的Datasheet PDF文件第3页浏览型号GS8640Z36GT-250IV的Datasheet PDF文件第4页浏览型号GS8640Z36GT-250IV的Datasheet PDF文件第5页浏览型号GS8640Z36GT-250IV的Datasheet PDF文件第6页浏览型号GS8640Z36GT-250IV的Datasheet PDF文件第7页 
Preliminary  
GS8640Z18/36T-xxxV  
250 MHz–167 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
72Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
The GS8640Z18/36T-xxxV may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, meaning that in addition to the  
rising edge triggered registers that capture input signals, the  
device incorporates a rising-edge-triggered output register. For  
read cycles, pipelined SRAM output data is temporarily stored  
by the edge triggered output register during the access cycle  
and then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS8640Z18/36T-xxxV is a 72Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8640Z18/36T-xxxV is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 100-pin TQFP package.  
Parameter Synopsis  
-250  
3.0  
4.0  
-200  
-167  
Unit  
t
3.0  
5.0  
3.5  
6.0  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
340  
410  
290  
350  
260  
305  
mA  
mA  
t
6.5  
6.5  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
KQ  
Flow Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
245  
280  
220  
250  
210  
240  
mA  
mA  
Rev: 1.01 6/2006  
1/22  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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中文翻译

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