Datasheet > GS8640FZ18T-7.5IT

GS8640FZ18T-7.5IT

更新时间： 2023-01-02 18:53:54

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
21页	255K
描述
ZBT SRAM, 4MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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GS8640FZ18T-7.5IT 数据手册

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GS8640FZ18/36T-5.5/6.5/7.5/8

5.5 ns–8 ns

100-Pin TQFP

Commercial Temp

Industrial Temp

72Mb Flow Through

Synchronous NBT SRAM

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

available bus bandwidth by eliminating the need to insert

deselect cycles when the device is switched from read to write

cycles.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

The GS8640FZ18/36T is configured to operate in Flow

Through mode.

Functional Description

The GS8640FZ18/36T is a 72Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other flow

through read/single late write SRAMs, allow utilization of all

The GS8640FZ18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

Parameter Synopsis

-5.5

-6.5

-7.5

-8

Unit

5.5

6.5

7.5

8.0

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x36)

285

330

245

280

220

250

210

240

Packages listed with the additional “G” designator are 6/6 RoHS compliant.

Rev: 1.01 10/2013

1/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...21

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