GS84018/32/36CGT-250/200/166/150
TQFP
Commercial Temp
Industrial Temp
250 MHz–150 MHz
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
counter may be configured to count in either linear or
Features
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
Flow Through/Pipeline Reads
• 2.5 V or 3.3 V I/O supply
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
SCD Pipelined Reads
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package
The GS84018/32/36CGT is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Functional Description
Applications
The GS84018/32/36CGT is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36CGT is
available in a JEDEC standard 100-lead TQFP package.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Controls
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Core and Interface Voltages
The GS84018/32/36CGT operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (V
) pins are used to de-couple
DDQ
output noise from the internal circuit.
Parameter Synopsis
-250
-200
-166
-150
Unit
tKQ
2.5
4.0
3.0
5.0
3.0
5.0
3.8
6.7
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
195
225
170
195
160
185
140
160
mA
mA
tKQ
5.5
5.5
6.5
6.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
160
180
140
160
135
155
128
145
mA
mA
Rev: 1.01 11/2014
1/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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