Datasheet > 存储 > SRAM> GS8342T09GE-200

GS8342T09GE-200

更新时间： 2024-01-06 17:16:01

品牌	Logo	应用领域
GSI		静态存储器双倍数据速率
页数	文件大小	规格书
37页	1722K
描述
36Mb SigmaCIO DDR-II Burst of 2 SRAM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS8342T09GE-200 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	37748736 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX9	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm

GS8342T09GE-200 数据手册

Preliminary

GS8342T08/09/18/36E-333/300/267*/250/200/167

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs

are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will

respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated

in the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is

possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer

and then execute the deselect command, returning the output drivers to high-Z. A high on the LD# pin prevents the RAM from

loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer

operations.

SigmaCIO DDR-II B2 SRAM Read Cycles

The SRAM executes pipelined reads. The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The

read command (LD# low and R/W# high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the

SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The

second beat of data is transferred on the next rising edge of C, for a total of two transfers per address load.

SigmaCIO DDR-II B2 SRAM Write Cycles

The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The SRAM executes "late write" data

transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write

command (LD# and R/W# low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM

captures data in on the next rising edge of K#, for a total of two transfers per address load.

Rev: 1.02 8/2005

7/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1...4 5 678 9 10...37

下载PDF

与GS8342T09GE-200相关器件

型号	品牌	描述	获取价格	数据表
GS8342T09GE-200I	GSI	36Mb SigmaCIO DDR-II Burst of 2 SRAM	获取价格
GS8342T09GE-250	GSI	36Mb SigmaCIO DDR-II Burst of 2 SRAM	获取价格
GS8342T09GE-250I	GSI	36Mb SigmaCIO DDR-II Burst of 2 SRAM	获取价格
GS8342T09GE-300	GSI	36Mb SigmaCIO DDR-II Burst of 2 SRAM	获取价格
GS8342T09GE-300I	GSI	36Mb SigmaCIO DDR-II Burst of 2 SRAM	获取价格
GS8342T09GE-300IT	GSI	Standard SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-	获取价格

与GS8342T09GE-200相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

17
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

16
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8342T09GE-200

GS8342T09GE-200 技术参数

GS8342T09GE-200 数据手册

与GS8342T09GE-200相关器件

与GS8342T09GE-200相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8342T09GE-200

GS8342T09GE-200 技术参数

GS8342T09GE-200 数据手册

与GS8342T09GE-200相关器件

与GS8342T09GE-200相关文章

您还可以找

您在本页遇到什么问题？