GS8342T08/09/18/36BD-400/350/333/300/250
Common I/O SigmaDDR-II B2 SRAM Truth Table
DQ
K
LD
R/W
Operation
n
A + 0
Hi-Z
A + 1
1
0
X
0
Hi-Z
Deselect
Write
D@Kn+1
Q@Kn+1
D@Kn+1
Q@Kn+2
0
1
or
Cn+1
or
Cn+2
Read
Note:
Q is controlled by K clocks if C clocks are not used.
Burst of 2 Byte Write Clock Truth Table
BW
BW
Current Operation
D
D
K
K
K
K
K
(t
)
(t
)
(t )
(t
)
(t
)
n + 1
n + 1½
n
n + 1
n + 1½
Write
T
T
F
T
F
D1
D2
X
Dx stored if BWn = 0 in both data transfers
Write
T
F
F
D1
X
Dx stored if BWn = 0 in 1st data transfer only
Write
D2
X
Dx stored if BWn = 0 in 2nd data transfer only
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.02b 8/2017
10/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.