Datasheet > GS832272C-133I

GS832272C-133I

更新时间： 2024-11-22 13:48:03

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
46页	3069K
描述
209 BGA

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数据手册

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GS832272C-133I 数据手册

GS832218(B/E)/GS832236(B/E)/GS832272(C)

119-, 165-, & 209-Pin BGA

Commercial Temp

Industrial Temp

250 MHz–133 MHz

2M x 18, 1M x 36, 512K x 72

36Mb S/DCD Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS832218/36/72 is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

• RoHS-compliant packages available

Functional Description

Applications

The GS832218/36/72 is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

_KQ(x18/x36)

2.5

3.0

4.0

2.7

3.0

4.4

3.0

5.0

3.5

6.0

3.8

6.7

4.0

7.5

_KQ(x72)

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x36)

Curr (x72)

285

350

440

265

320

410

245

295

370

220

260

320

210 185

240 215

300 265

t_KQ

6.5

7.0

7.5

8.0

8.5

tCycle

Flow

Through

2-1-1-1

Curr (x18)

Curr (x36)

Curr (x72)

205

235

315

195

225

295

185

210

265

175

200

255

165 155

190 175

240 230

Rev: 1.07a 12/2007

1/46

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...46

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与GS832272C-133I相关器件

型号	品牌	获取价格	描述	数据表
GS832272C-133IV	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-133IVT	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-133T	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-133V	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-150	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-150I	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-150IV	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-150V	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-150VT	GSI	获取价格	Cache SRAM, 512KX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-166	GSI	获取价格	Cache SRAM, 512KX72, 8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

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