Datasheet > GS832272C-225M

GS832272C-225M

更新时间： 2024-11-26 14:57:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
28页	508K
描述
209 BGA

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GS832272C-225M 技术参数

是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA209,11X19,40
针数：	209	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.39	最长访问时间：	7 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	最大时钟频率 (fCLK)：	225 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B209
长度：	22 mm	内存密度：	37748736 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	72
功能数量：	1	端子数量：	209
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	512KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA209,11X19,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	电源：	2.5/3.3 V
认证状态：	Not Qualified	座面最大高度：	1.7 mm
最大待机电流：	0.2 A	最小待机电流：	2.3 V
子类别：	SRAMs	最大压摆率：	0.39 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	14 mm
Base Number Matches：	1

GS832272C-225M 数据手册

GS832272C-225M

225 MHz

512K x 72

36Mb S/DCD Sync Burst SRAMs

209-Pin BGA

Military Temp

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

Features

• Military Temperature Range

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

SCD and DCD Pipelined Reads

The GS832272C-225M is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 209-bump BGA package

Functional Description

Applications

The GS832272C-225M is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Controls

FLXDrive™

Addresses, data I/Os, chip enable (E1, E2, and E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a positive-

edge-triggered clock input (CK). Output enable (G) and power

down control (ZZ) are asynchronous inputs. Burst cycles can be

initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be configured

to count in either linear or interleave order with the Linear Burst

Order (LBO) input. The Burst function need not be used. New

addresses can be loaded on every cycle with no degradation of

chip performance.

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS832272C-225M operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate output

power (V_DDQ) pins are used to decouple output noise from the

internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-225M

Unit

t_KQ

tCycle

3.0

4.4

Pipeline

3-1-1-1

Curr (x72)

t_KQ

460

7.0

Flow Through

2-1-1-1

tCycle

Curr (x72)

360

Rev: 1.01 10/2016

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

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与GS832272C-225M相关器件

型号	品牌	获取价格	描述	数据表
GS832272C-225MT	GSI	获取价格	Cache SRAM, 512KX72, 7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-225V	GSI	获取价格	Cache SRAM, 512KX72, 7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-250	GSI	获取价格	Cache SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-250I	GSI	获取价格	暂无描述
GS832272C-250IT	GSI	获取价格	Cache SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-250IV	GSI	获取价格	209 BGA
GS832272C-250T	GSI	获取价格	Cache SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-250V	GSI	获取价格	Cache SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272C-250VT	GSI	获取价格	Cache SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS832272GC-133	GSI	获取价格	209 BGA

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