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GS8321Z18AGD-200IV PDF预览

GS8321Z18AGD-200IV

更新时间： 2024-02-05 03:20:53
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
31页 465K
描述
ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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GS8321Z18AGD-200IV 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41Factory Lead Time：8 weeks
风险等级：5.14最长访问时间：6.5 ns
其他特性：ALSO OPERATES AT 2.5V SUPPLY, PIPELINED ARCHITECTURE, FLOW THROUGH最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：1.8/2.5 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.04 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.185 mA最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

GS8321Z18AGD-200IV 数据手册

 浏览型号GS8321Z18AGD-200IV的Datasheet PDF文件第4页浏览型号GS8321Z18AGD-200IV的Datasheet PDF文件第5页浏览型号GS8321Z18AGD-200IV的Datasheet PDF文件第6页浏览型号GS8321Z18AGD-200IV的Datasheet PDF文件第8页浏览型号GS8321Z18AGD-200IV的Datasheet PDF文件第9页浏览型号GS8321Z18AGD-200IV的Datasheet PDF文件第10页 
GS8321Z18/32/36AD-xxxV  
Functional Details  
Clocking  
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to  
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.  
Pipeline Mode Read and Write Operations  
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle  
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device  
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable  
inputs will deactivate the device.  
Function  
Read  
W
H
L
BA  
X
BB  
X
BC  
X
BD  
X
Write Byte “a”  
Write Byte “b”  
Write Byte “c”  
Write Byte “d”  
Write all Bytes  
Write Abort/NOP  
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three  
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address  
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control  
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At  
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.  
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The  
Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle  
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the  
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising  
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the  
third rising edge of clock.  
Flow Through Mode Read and Write Operations  
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use  
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new  
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow  
Through mode the read pipeline is one cycle shorter than in Pipeline mode.  
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability  
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late  
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address  
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of  
clock.  
Rev: 1.03 8/2013  
7/31  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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