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GS8320Z36T-200I PDF预览

GS8320Z36T-200I

更新时间： 2024-02-16 18:12:01
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
24页 452K
描述
36Mb Pipelined and Flow Through Synchronous NBT SRAMs

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GS8320Z36T-200I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.3最长访问时间：6.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLYJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：37748736 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS8320Z36T-200I 数据手册

 浏览型号GS8320Z36T-200I的Datasheet PDF文件第4页浏览型号GS8320Z36T-200I的Datasheet PDF文件第5页浏览型号GS8320Z36T-200I的Datasheet PDF文件第6页浏览型号GS8320Z36T-200I的Datasheet PDF文件第8页浏览型号GS8320Z36T-200I的Datasheet PDF文件第9页浏览型号GS8320Z36T-200I的Datasheet PDF文件第10页 
Preliminary  
GS8320Z18/36T-250/225/200/166/150/133  
Synchronous Truth Table  
Operation  
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
NOP/Read, Begin Burst  
R
B
R
B
W
B
B
D
D
D
External  
Next  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L
L
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
X
L
H
X
H
X
H
X
X
X
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
Q
Q
1,10  
2
External  
Next  
H
H
X
X
X
X
X
X
High-Z  
Dummy Read, Continue Burst  
Write Cycle, Begin Burst  
H
L
X
L
X
L
High-Z 1,2,10  
External  
Next  
D
D
3
Write Cycle, Continue Burst  
Write Abort, Continue Burst  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
H
H
L
X
X
X
X
X
L
X
X
H
X
X
X
X
X
H
X
1,3,10  
Next  
H
X
X
X
High-Z 1,2,3,10  
High-Z  
None  
None  
L
High-Z  
None  
L
High-Z  
1
Deselect Cycle  
D
D
None  
L-H  
L
L
L
H
L
H
L
X
L
High-Z  
Deselect Cycle, Continue  
Sleep Mode  
None  
None  
L-H  
X
L
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
High-Z  
High-Z  
-
1
4
Clock Edge Ignore, Stall  
Current  
L-H  
Notes:  
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-  
lect cycle is executed first.  
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W  
pin is sampled low but no Byte Write pins are active so no write operation is performed.  
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during  
write cycles.  
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus  
will remain in High Z.  
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write  
signals are Low  
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.  
7. Wait states can be inserted by setting CKE high.  
8. This device contains circuitry that ensures all outputs are in High Z during power-up.  
9. A 2-bit burst counter is incorporated.  
10. The address counter is incriminated for all Burst continue cycles.  
Rev: 1.03 10/2004  
7/24  
© 2001, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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