Datasheet > GS832032AGT-200

GS832032AGT-200

更新时间： 2024-11-30 00:44:03

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
24页	253K
描述
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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技术参数
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GS832032AGT-200 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	Factory Lead Time：	8 weeks
风险等级：	5.32	最长访问时间：	6.5 ns
其他特性：	ALSO OPERATES AT 3.3; SYNCHRONOUS BURST	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	33554432 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
功能数量：	1	端子数量：	100
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：		组织：	1MX32
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS832032AGT-200 数据手册

GS832018/32/36AGT-400/375/333/250/200/150

400 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• Automatic power-down for portable applications

• RoHS-compliant 100-lead TQFP package

Functional Description

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS832018/32/36AGT is a 37,748,736-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Core and Interface Voltages

The GS832018/32/36AGT operates on a 3.3 V or 2.5 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-400

-375

-333

-250

-200

-150

Unit

2.5

2.66

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

395

475

390

455

355

415

280

335

240

280

205

230

4.0

4.2

4.5

5.5

6.5

7.5

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

290

335

275

320

260

305

235

270

200

240

190

220

Rev: 1.03 8/2013

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS832032AGT-200相关器件

型号	品牌	获取价格	描述	数据表
GS832032AGT-200I	GSI	获取价格	100 TQFP
GS832032AGT-200IV	GSI	获取价格	Cache SRAM, 1MX32, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-200V	GSI	获取价格	Cache SRAM, 1MX32, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-250	GSI	获取价格	Cache SRAM, 1MX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-250I	GSI	获取价格	100 TQFP
GS832032AGT-250IV	GSI	获取价格	100 TQFP
GS832032AGT-250V	GSI	获取价格	Cache SRAM, 1MX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-333	GSI	获取价格	Cache SRAM, 1MX32, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-333I	GSI	获取价格	Cache SRAM, 1MX32, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-333IV	GSI	获取价格	100 TQFP

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