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GS832032AGT-200V PDF预览

GS832032AGT-200V

更新时间： 2024-11-29 19:46:39
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
22页 330K
描述
Cache SRAM, 1MX32, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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中文翻译

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GS832032AGT-200V 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BFactory Lead Time：8 weeks
风险等级：5.32最长访问时间：6.5 ns
其他特性：ALSO OPERTAES AT 2.5, SYNCHRONOUS BURSTJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：33554432 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：100
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：组织：1MX32
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS832032AGT-200V 数据手册

 浏览型号GS832032AGT-200V的Datasheet PDF文件第2页浏览型号GS832032AGT-200V的Datasheet PDF文件第3页浏览型号GS832032AGT-200V的Datasheet PDF文件第4页浏览型号GS832032AGT-200V的Datasheet PDF文件第5页浏览型号GS832032AGT-200V的Datasheet PDF文件第6页浏览型号GS832032AGT-200V的Datasheet PDF文件第7页 
GS832018/32/36AGT-xxxV  
333 MHz–150 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
2M x 18, 1M x 32, 1M x 36  
36Mb Sync Burst SRAMs  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Single Cycle Deselect (SCD) operation  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
• Automatic power-down for portable applications  
• RoHS-compliant 100-lead TQFP package available  
Functional Description  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Applications  
The GS832018/32/36AGT-xxxV is a 37,748,736-bit high  
performance synchronous SRAM with a 2-bit burst address  
counter. Although of a type originally developed for Level 2  
Cache applications supporting high performance CPUs, the  
device now finds application in synchronous SRAM  
applications, ranging from DSP main store to networking chip  
set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
Core and Interface Voltages  
The GS832018/32/36AGT-xxxV operates on a 1.8 V power  
supply. All input are 1.8 V compatible. Separate output power  
(V  
) pins are used to decouple output noise from the  
DDQ  
internal circuits and are 1.8 V compatible.  
Parameter Synopsis  
-333  
-250  
-200  
-150  
Unit  
t
2.5  
3.3  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
365  
425  
290  
345  
250  
290  
215  
240  
mA  
mA  
t
4.5  
4.5  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
270  
315  
245  
280  
210  
250  
200  
230  
mA  
mA  
Rev: 1.03 8/2013  
1/22  
© 2011, GSI Technology  
1234567...22

中文翻译

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与GS832032AGT-200V相关器件

型号 品牌 获取价格 描述 数据表
GS832032AGT-250 GSI

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 		Cache SRAM, 1MX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-250I GSI

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GS832032AGT-250IV GSI

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 		100 TQFP
GS832032AGT-250V GSI

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 		Cache SRAM, 1MX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-333 GSI

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 		Cache SRAM, 1MX32, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-333I GSI

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 		Cache SRAM, 1MX32, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832032AGT-333IV GSI

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 		100 TQFP
GS832032AGT-333V GSI

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 		100 TQFP
GS832032AGT-375 GSI

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 		2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832032AGT-375I GSI

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 		2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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