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GS8161Z36DGD-200IV PDF预览

GS8161Z36DGD-200IV

更新时间： 2024-11-19 13:22:15
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
36页 493K
描述
ZBT SRAM, 512KX36, 6.5ns, CMOS, PBGA165, ROHS COMPLIANT, FPBGA-165

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GS8161Z36DGD-200IV 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：BGA包装说明：LBGA,
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：10 weeks风险等级：5.22
Is Samacsys：N最长访问时间：6.5 ns
其他特性：FLOW THROUGH AND PIPELINED ARCHITECTURE, ALSO OPERATES AT 2.5VJESD-30 代码：R-PBGA-B165
长度：15 mm内存密度：18874368 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.4 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

GS8161Z36DGD-200IV 数据手册

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GS8161ZxxD(GT/D)-xxxV  
333 MHz–150 MHz  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable, ZZ and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• User-configurable Pipeline and Flow Through mode  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization  
• Fully pin-compatible with both pipelined and flow through  
NtRAM™, NoBL™ and ZBT™ SRAMs  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and  
144Mb devices  
The GS8161ZxxD(GT/D)-xxxV may be configured by the user  
to operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising-edge-triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ pin for automatic power-down  
• JEDEC-standard 165-bump BGA package  
• RoHS-compliant 100-pin TQFP and BGA packages available  
Functional Description  
The GS8161ZxxD(GT/D)-xxxV is an 18Mbit Synchronous  
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL  
or other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8161ZxxD(GT/D)-xxxV is implemented with GSI's  
high performance CMOS technology and is available in  
JEDEC-standard 165-bump FP-BGA package.  
Parameter Synopsis  
-333  
-250  
-200  
-150  
Unit  
t
3.0  
3.0  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
305  
360  
245  
285  
205  
235  
175  
195  
mA  
mA  
t
5.0  
5.0  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
235  
265  
215  
245  
205  
225  
190  
205  
mA  
mA  
Rev: 1.03b 9/2013  
1/36  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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与GS8161Z36DGD-200IV相关器件

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 		ZBT SRAM, 512KX36, 6.5ns, CMOS, PBGA165, ROHS COMPLIANT, FPBGA-165
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GS8161Z36DGD-200VT GSI

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GS8161Z36DGD-250I GSI

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GS8161Z36DGD-250IV GSI

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 		ZBT SRAM, 512KX36, 5.5ns, CMOS, PBGA165, ROHS COMPLIANT, FPBGA-165
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GS8161Z36DGD-333 GSI

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GS8161Z36DGD-333I GSI

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 		165 BGA
GS8161Z36DGD-333IV GSI

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 		ZBT SRAM, 512KX36, 5ns, CMOS, PBGA165, ROHS COMPLIANT, FPBGA-165

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