Datasheet > 存储 > SRAM> GS8161Z36DGT-150IV

GS8161Z36DGT-150IV

更新时间： 2024-11-20 13:47:59

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
36页	493K
描述
100 TQFP

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GS8161ZxxD(GT/D)-xxxV

333 MHz–150 MHz

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and

144Mb devices

The GS8161ZxxD(GT/D)-xxxV may be configured by the user

to operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump BGA package

• RoHS-compliant 100-pin TQFP and BGA packages available

Functional Description

The GS8161ZxxD(GT/D)-xxxV is an 18Mbit Synchronous

Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL

or other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8161ZxxD(GT/D)-xxxV is implemented with GSI's

high performance CMOS technology and is available in

JEDEC-standard 165-bump FP-BGA package.

Parameter Synopsis

-333

-250

-200

-150

Unit

3.0

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x36)

305

360

245

285

205

235

175

195

5.0

5.5

6.5

7.5

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x36)

235

265

215

245

205

225

190

205

Rev: 1.03b 9/2013

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...36

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与GS8161Z36DGT-150IV相关器件

型号	品牌	获取价格	描述	数据表
GS8161Z36DGT-150V	GSI	获取价格	100 TQFP
GS8161Z36DGT-200	GSI	获取价格	ZBT SRAM, 512KX36, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DGT-200FLASE	GSI	获取价格	ZBT SRAM
GS8161Z36DGT-200I	GSI	获取价格	100 TQFP
GS8161Z36DGT-200ITFLASE	GSI	获取价格	ZBT SRAM
GS8161Z36DGT-200IV	GSI	获取价格	ZBT SRAM, 512KX36, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DGT-200V	GSI	获取价格	100 TQFP
GS8161Z36DGT-250	GSI	获取价格	100 TQFP
GS8161Z36DGT-250I	GSI	获取价格	ZBT SRAM, 512KX36, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DGT-250IFLASE	GSI	获取价格	ZBT SRAM

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