Datasheet > GS8161Z36D-250I

GS8161Z36D-250I

更新时间： 2024-11-19 07:02:07

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
36页	901K
描述
18Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS8161Z36D-250I 数据手册

GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)

100-Pin TQFP

Commercial Temp

Industrial Temp

250 MHz–133 MHz

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA

packages

The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) may

be configured by the user to operate in Pipeline or Flow

Through mode. Operating as a pipelined synchronous device,

in addition to the rising-edge-triggered registers that capture

input signals, the device incorporates a rising-edge-triggered

output register. For read cycles, pipelined SRAM output data is

temporarily stored by the edge triggered output register during

the access cycle and then released to the output drivers at the

next rising edge of clock.

Functional Description

The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is an

18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like

ZBT, NtRAM, NoBL or other pipelined read/double late write

or flow through read/single late write SRAMs, allow

utilization of all available bus bandwidth by eliminating the

need to insert deselect cycles when the device is switched from

read to write cycles.

The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is

implemented with GSI's high performance CMOS technology

and is available in JEDEC-standard 100-pin TQFP and

165-bump FP-BGA packages.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

tCycle

Curr ^(x18)

280 255 230 200 185 165 mA

3.3 V

2.5 V

Curr (x32/x36) 330 300 270 230 215 190 mA

Curr ^(x18)275 250 230 195 180 165 mA

Curr (x32/x36) 320 295 265 225 210 185 mA

Flow

Through

2-1-1-1

5.5 6.0 6.5 7.0 7.5 8.5 ns

tCycle

Curr ^(x18)

175 165 160 150 145 135 mA

3.3 V

2.5 V

Curr (x32/x36) 200 190 180 170 165 150 mA

Curr ^(x18)175 165 160 150 145 135 mA

Curr (x32/x36) 200 190 180 170 165 150 mA

Rev: 2.15 11/2004

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...36

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与GS8161Z36D-250I相关器件

型号	品牌	获取价格	描述	数据表
GS8161Z36D-250IT	GSI	获取价格	18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8161Z36D-250T	GSI	获取价格	18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8161Z36DD-150	GSI	获取价格	165 BGA
GS8161Z36DD-150I	GSI	获取价格	165 BGA
GS8161Z36DD-150IV	GSI	获取价格	ZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA165, FPBGA-165
GS8161Z36DD-150V	GSI	获取价格	165 BGA
GS8161Z36DD-200	GSI	获取价格	165 BGA
GS8161Z36DD-200I	GSI	获取价格	165 BGA
GS8161Z36DD-200IV	GSI	获取价格	165 BGA
GS8161Z36DD-200V	GSI	获取价格	165 BGA

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