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GS8161E32DGD-375

更新时间： 2024-10-28 13:47:59
品牌 Logo 应用领域
GSI /
页数 文件大小 规格书
37页 320K
描述
165 BGA

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GS8161E32DGD-375 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LBGA,
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：10 weeks风险等级：5.31
最长访问时间：4.2 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：R-PBGA-B165长度：15 mm
内存密度：16777216 bit内存集成电路类型：CACHE SRAM
内存宽度：32功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX32封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

GS8161E32DGD-375 数据手册

 浏览型号GS8161E32DGD-375的Datasheet PDF文件第2页浏览型号GS8161E32DGD-375的Datasheet PDF文件第3页浏览型号GS8161E32DGD-375的Datasheet PDF文件第4页浏览型号GS8161E32DGD-375的Datasheet PDF文件第5页浏览型号GS8161E32DGD-375的Datasheet PDF文件第6页浏览型号GS8161E32DGD-375的Datasheet PDF文件第7页 
GS8161E18D(GT/D)/GS8161E32D(D)/GS8161E36D(GT/D)  
400 MHz–150 MHz  
2.5 V or 3.3 V VDD  
2.5 V or 3.3 V I/O  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
1M x 18, 512K x 32, 512K x 36  
18Mb SyncBurst SRAMs  
Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline operation  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 165-bump BGA package  
• RoHS-compliant 100-pin TQFP and 165-bump BGA available  
DCD Pipelined Reads  
The GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D) is  
a DCD (Dual Cycle Deselect) pipelined synchronous SRAM.  
SCD (Single Cycle Deselect) versions are also available. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. DCD RAMs hold the deselect command for one  
full cycle and then begin turning off their outputs just after the  
second rising edge of clock.  
Functional Description  
Applications  
The GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D) is  
an 18,874,368-bit high performance synchronous SRAM with  
a 2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,  
BW, GW) are synchronous and are controlled by a positive-  
edge-triggered clock input (CK). Output enable (G) and power  
down control (ZZ) are asynchronous inputs. Burst cycles can  
be initiated with either ADSP or ADSC inputs. In Burst mode,  
subsequent burst addresses are generated internally and are  
controlled by ADV. The burst address counter may be  
configured to count in either linear or interleave order with the  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D)  
operates on a 3.3 V or 2.5 V power supply. All input are 3.3 V  
and 2.5 V compatible. Separate output power (V  
) pins are  
DDQ  
used to decouple output noise from the internal circuits and are  
3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-400  
-375  
-333  
-250  
-200  
-150  
Unit  
t
2.5  
2.5  
2.5  
2.66  
2.5  
3.3  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
370  
430  
350  
410  
310  
365  
250  
290  
210  
240  
185  
200  
mA  
mA  
t
4.0  
4.0  
4.2  
4.2  
4.5  
4.5  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
275  
315  
265  
300  
255  
285  
220  
250  
205  
225  
190  
205  
mA  
mA  
Rev: 1.03b 9/2013  
1/37  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS8161E32DGD-400I GSI

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GS8161E32GD-150T GSI

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GS8161E32GD-200I GSI

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 		Cache SRAM, 512KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E32GD-200IT GSI

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 		Cache SRAM, 512KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E32GD-200T GSI

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 		Cache SRAM, 512KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161E32GD-225 GSI

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