5秒后页面跳转
GS81302T06E-375IT PDF预览

GS81302T06E-375IT

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
GSI 双倍数据速率静态存储器
页数 文件大小 规格书
32页 454K
描述
DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

GS81302T06E-375IT 数据手册

 浏览型号GS81302T06E-375IT的Datasheet PDF文件第2页浏览型号GS81302T06E-375IT的Datasheet PDF文件第3页浏览型号GS81302T06E-375IT的Datasheet PDF文件第4页浏览型号GS81302T06E-375IT的Datasheet PDF文件第5页浏览型号GS81302T06E-375IT的Datasheet PDF文件第6页浏览型号GS81302T06E-375IT的Datasheet PDF文件第7页 
Preliminary  
GS81302T06/11/20/38E-450/400/375/333/300  
450 MHz–300 MHz  
144Mb SigmaDDRTM-II+  
Burst of 2 SRAM  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V or 1.5 V I/O  
Features  
• 2.5 Clock Latency  
TM  
• Simultaneous Read and Write SigmaDDR Interface  
• JEDEC-standard pinout and package  
• Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 2 Read and Write  
• On-Die Termination (ODT) on Data (D), Byte Write (BW),  
and Clock (K, K) inputs  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• Data Valid Pin (QVLD) Support  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Bottom View  
165-Bump, 15 mm x 17 mm BGA  
1 mm Bump Pitch, 11 x 15 Bump Array  
Clocking and Addressing Schemes  
SigmaDDR-IIFamily Overview  
The GS81302T06/11/20/38E SigmaDDR-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
The GS81302T06/11/20/38E are built in compliance with the  
SigmaDDR-II+ SRAM pinout standard for Common I/O  
synchronous SRAMs. They are 150,994,944-bit (144Mb)  
SRAMs. The GS81302T06/11/20/38E SigmaDDR-II+  
SRAMs are just one element in a family of low power, low  
voltage HSTL I/O SRAMs designed to operate at the speeds  
needed to implement economical high performance  
networking systems.  
Because Common I/O SigmaDDR-II+ RAMs always transfer  
data in two packets, A0 is internally set to 0 for the first read  
or write transfer, and automatically incremented by 1 for the  
next transfer. Because the LSB is tied off internally, the  
address field of a SigmaDDR-II+ B2 RAM is always one  
address pin less than the advertised index depth (e.g., the 8M x  
18 has a 4M addressable index).  
Parameter Synopsis  
-450  
2.2 ns  
0.37 ns  
-400  
2.5 ns  
0.45 ns  
-375  
2.66 ns  
0.45 ns  
-333  
-300  
3.3 ns  
0.45 ns  
tKHKH  
tKHQV  
3.0 ns  
0.45 ns  
Rev: 1.01a 6/2010  
1/32  
© 2009, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

与GS81302T06E-375IT相关器件

型号 品牌 获取价格 描述 数据表
GS81302T06E-375T GSI

获取价格

DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS81302T06E-400 GSI

获取价格

165 BGA
GS81302T06E-400I GSI

获取价格

165 BGA
GS81302T06E-450 GSI

获取价格

165 BGA
GS81302T06E-450I GSI

获取价格

165 BGA
GS81302T06E-500 GSI

获取价格

165 BGA
GS81302T06E-500I GSI

获取价格

165 BGA
GS81302T06E-500T GSI

获取价格

DDR SRAM, 16MX8, 0.37ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS81302T06GE-300I GSI

获取价格

DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS81302T06GE-300T GSI

获取价格

DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165