Datasheet > GS81282Z36GB-333V

GS81282Z36GB-333V

更新时间： 2024-11-28 00:43:31

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
33页	439K
描述
144Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS81282Z18/36(GB/GD)-xxxV

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

333 MHz–200 MHz

144Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Features

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb

devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

The GS81282Z18/36 may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising edge triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge-triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

• RoHS-compliant 119- and 165-bump BGA packages

Functional Description

The GS81282Z18/36 is a 144Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS81282Z18/362 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump or 165-bump BGA package.

Parameter Synopsis

-333

2.5

3.0

-250

-200

Unit

t_KQ

tCycle

2.5

4.0

3.0

5.0

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

530

580

430

460

360

390

t_KQ

tCycle

4.5

5.5

6.5

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

400

420

360

380

285

320

Rev: 1.01 5/2017

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...33

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与GS81282Z36GB-333V相关器件

型号	品牌	获取价格	描述	数据表
GS81282Z36GB-400	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GB-400I	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-200	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-200I	GSI	获取价格	165 BGA
GS81282Z36GD-200IV	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-200V	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-250	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-250I	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-250IV	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM
GS81282Z36GD-250V	GSI	获取价格	144Mb Pipelined and Flow Through Synchronous NBT SRAM

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