Datasheet > GS8128418B-200IV

GS8128418B-200IV

更新时间： 2023-02-26 15:46:22

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
30页	652K
描述
Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119

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数据手册

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GS8128418B-200IV 数据手册

GS8128418/36B-xxxV

119-Pin BGA

Commercial Temp

Industrial Temp

200 MHz–167 MHz

8M x 18, 4M x 36,

144Mb S/DCD Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-BGA package

• RoHS-compliant 119-BGA packages available

SCD and DCD Pipelined Reads

The GS8128418/36B-xxxV is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Functional Description

Applications

The GS8128418/36B-xxxV is a 150,994,944-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

FLXDrive™

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS8128418/36B-xxxV operates on a 1.8 V or 2.5 V power

supply. All inputs are 1.8 V or 2.5 V compatible. Separate output

power (V_DDQ) pins are used to decouple output noise from the

internal circuits and are 1.8 V or 2.5 V compatible.

Parameter Synopsis

-200

-167

Unit

t_KQ

)

3.0

5.0

3.4

6.0

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x36)

420

480

385

430

t_KQ

7.5

8.0

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x36)

340

370

330

360

Rev: 1.02 7/2010

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...30

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与GS8128418B-200IV相关器件

型号	品牌	获取价格	描述	数据表
GS8128418B-200T	GSI	获取价格	Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS8128418B-200V	GSI	获取价格	Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS8128418B-200VT	GSI	获取价格	Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS8128418B-250	GSI	获取价格	Cache SRAM, 8MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS8128418B-250I	GSI	获取价格	Cache SRAM, 8MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS8128418B-300IT	GSI	获取价格	Cache SRAM, 8MX18, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS8128418GB-167	GSI	获取价格	Cache SRAM, 8MX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-11
GS8128418GB-167I	GSI	获取价格	119 BGA
GS8128418GB-167IT	GSI	获取价格	Cache SRAM, 8MX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-11
GS8128418GB-167IV	GSI	获取价格	Cache SRAM, 8MX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-11

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