GS74104ATP/J/X
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
6, 7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
1M x 4
4Mb Asynchronous SRAM
SOJ 1M x 4-Pin Configuraton
Features
• Fast access time: 6, 7, 8, 10, 12 ns
• CMOS low power operation: 155/135/120/95/85 mA at
minimum cycle time
32
A5
1
A4
31
2
A3
A6
30
A7
3
A2
• Single 3.3 V power supply
29
4
A1
A8
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
28
A9
5
A0
27
6
CE
OE
32-pin
26
7
DQ1
VDD
VSS
DQ2
WE
A19
A18
A17
A16
A15
DQ4
25
8
VSS
VDD
DQ3
A10
A11
A12
A13
A14
NC
400 mil SOJ
24
23
22
21
20
19
18
17
9
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
10
11
12
13
14
15
16
Description
The GS74104A is a high speed CMOS Static RAM organized
as 1,048,576 words by 4 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74104A is available in 400 mil SOJ, 400
mil TSOP Type-II, and 6 mm x 10 mm FP-BGA packages.
FP-BGA 256K x 16 Bump Configuration (Package X)
1
2
3
4
5
6
A
B
C
D
E
F
LB
OE
A0
A3
A1
A4
A6
A7
A2
NC
DQ16 UB
CE DQ1
DQ2 DQ3
DQ4 VDD
Pin Descriptions
DQ14 DQ15 A5
VSS DQ13 A17
VDD DQ12 NC
DQ11 DQ10 A8
Symbol
A0–A19
DQ1–DQ4
CE
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
A16 DQ5 VSS
A9
DQ7 DQ6
WE DQ8
WE
G
H
DQ9 NC
NC A12
A10
A13
A11
A14
OE
V
A15
NC
DD
V
Ground
SS
NC
No connect
6 x 10 mm Bump Pitch
Rev: 1.02 3/2002
1/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.