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GS1284218GB-200IT PDF预览

GS1284218GB-200IT

更新时间： 2024-11-21 19:51:27
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
30页 678K
描述
Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119

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GS1284218GB-200IT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.55
最长访问时间：7.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE, ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：150994944 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：8MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.99 mm最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS1284218GB-200IT 数据手册

 浏览型号GS1284218GB-200IT的Datasheet PDF文件第2页浏览型号GS1284218GB-200IT的Datasheet PDF文件第3页浏览型号GS1284218GB-200IT的Datasheet PDF文件第4页浏览型号GS1284218GB-200IT的Datasheet PDF文件第5页浏览型号GS1284218GB-200IT的Datasheet PDF文件第6页浏览型号GS1284218GB-200IT的Datasheet PDF文件第7页 
Preliminary  
GS8128418/36B-250/200/167  
119-BGA  
Commercial Temp  
Industrial Temp  
250 MHz–167 MHz  
8M x 18,4M x 36  
144Mb S/DCD Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
either linear or interleave order with the Linear Burst Order (LBO)  
input. The Burst function need not be used. New addresses can be  
loaded on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline operation  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 2.5 V +10%/–10% core power supply  
• 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to SCD x18/x36 Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by the  
user via the FT mode . Holding the FT mode pin low places the  
RAM in Flow Through mode, causing output data to bypass the  
Data Output Register. Holding FT high places the RAM in  
Pipeline mode, activating the rising-edge-triggered Data Output  
Register.  
SCD and DCD Pipelined Reads  
The GS8128418/36 is a SCD (Single Cycle Deselect) and DCD  
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. SCD SRAMs pipeline deselect commands one stage  
less than read commands. SCD RAMs begin turning off their  
outputs immediately after the deselect command has been  
captured in the input registers. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock. The user may  
configure this SRAM for either mode of operation using the SCD  
mode input.  
• ZZ pin for automatic power-down  
• JEDEC-standard 119-bump BGA package  
• RoHS-compliant 119-bump BGA packages available  
Functional Description  
Applications  
The GS8128418/36 is a 150,994,944-bit high performance  
synchronous SRAM with a 2-bit burst address counter. Although  
of a type originally developed for Level 2 Cache applications  
supporting high performance CPUs, the device now finds  
application in synchronous SRAM applications, ranging from  
DSP main store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write control  
inputs.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,  
GW) are synchronous and are controlled by a positive-edge-  
triggered clock input (CK). Output enable (G) and power down  
control (ZZ) are asynchronous inputs. Burst cycles can be initiated  
with either ADSP or ADSC inputs. In Burst mode, subsequent  
burst addresses are generated internally and are controlled by  
ADV. The burst address counter may be configured to count in  
FLXDrive™  
The ZQ pin allows selection between high drive strength (ZQ low)  
for multi-drop bus applications and normal drive strength (ZQ  
floating or high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Parameter Synopsis  
-250  
-200  
-167  
Unit  
tKQ(x18/x36)  
tCycle  
2.5  
4.0  
3.0  
5.0  
3.4  
6.0  
ns  
ns  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
480  
550  
420  
480  
385  
430  
mA  
mA  
tKQ  
6.5  
6.5  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x36)  
370  
405  
340  
370  
330  
360  
mA  
mA  
Rev: 1.02 3/2010  
1/30  
© 2007, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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