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GS1284218GB-250I PDF预览

GS1284218GB-250I

更新时间： 2024-11-22 01:06:35
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
35页 448K
描述
288Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS1284218GB-250I 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.77其他特性：IT ALSO OPERATES AT 3 V TO 3.6 V SUPPLY VOLTAGE
JESD-30 代码：R-PBGA-B119长度：22 mm
内存密度：150994944 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：119字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
组织：8MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.99 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS1284218GB-250I 数据手册

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GS82564Z18/36(GB/GD)  
119- & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
400 MHz–200 MHz  
288Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Features  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb  
devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
The GS82564Z18/36 may be configured by the user to operate  
in Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, in addition to the rising-edge-triggered  
registers that capture input signals, the device incorporates a  
rising edge triggered output register. For read cycles, pipelined  
SRAM output data is temporarily stored by the edge-triggered  
output register during the access cycle and then released to the  
output drivers at the next rising edge of clock.  
• RoHS-compliant 119- and 165-bump BGA packages  
Functional Description  
The GS82564Z18/36 is a 288Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS82564Z18/362 is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump or 165-bump BGA package.  
Parameter Synopsis  
-400  
-333  
-250  
-200  
Unit  
tKQ  
tCycle  
2.5  
2.5  
2.5  
3.0  
2.5  
4.0  
3.0  
5.0  
ns  
ns  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
730  
820  
650  
720  
540  
590  
520  
470  
mA  
mA  
tKQ  
tCycle  
4.0  
4.0  
4.5  
4.5  
5.5  
5.5  
6.5  
6.5  
ns  
ns  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x36)  
520  
540  
500  
550  
440  
500  
410  
470  
mA  
mA  
Rev: 1.02 5/2017  
1/34  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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