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GPC5643LF2MLQ1 PDF预览

GPC5643LF2MLQ1

更新时间: 2024-03-03 10:07:49
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
136页 1175K
描述
NXP 32-bit MCU, Dual Power Arch, 1MB Flash, 120MHz, -40/+125degC, Automotive Grade, QFP 144

GPC5643LF2MLQ1 数据手册

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Introduction  
1.5.2  
Crossbar switch (XBAR)  
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The  
crossbar supports a 32-bit address bus width and a 64-bit data bus width.  
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers  
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master  
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting  
that slave port are stalled until the higher priority master completes its transactions.  
The crossbar provides the following features:  
4 masters and 3 slaves supported per each replicated crossbar  
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D  
access (2 masters), one eDMA, one FlexRay  
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum  
flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1  
redundant peripheral bus bridge  
32-bit address bus and 64-bit data bus  
Programmable arbitration priority  
— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,  
based upon the ID of the last master to be granted access or a priority order can be assigned by software at  
application run time  
Temporary dynamic priority elevation of masters  
The XBAR is replicated for each processing channel.  
1.5.3  
Memory Protection Unit (MPU)  
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be  
assigned different access rights to each region.  
16-region MPU with concurrent checks against each master access  
32-byte granularity for protected address region  
The memory protection unit is replicated for each processing channel.  
1.5.4  
Enhanced Direct Memory Access (eDMA)  
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data  
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture  
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,  
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation  
is used to minimize the overall block size.  
The eDMA module provides the following features:  
16 channels supporting 8-, 16-, and 32-bit value single or block transfers  
Support variable sized queues and circular buffered queue  
Source and destination address registers independently configured to post-increment or stay constant  
Support major and minor loop offset  
Support minor and major loop done signals  
DMA task initiated either by hardware requestor or by software  
Each DMA task can optionally generate an interrupt at completion and retirement of the task  
Signal to indicate closure of last minor loop  
MPC5643L Microcontroller Data Sheet, Rev. 10  
8
NXP Semiconductors  

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