Datasheet > GPC5643LF2MLQ1

GPC5643LF2MLQ1

更新时间： 2024-03-03 10:07:49

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
136页	1175K
描述
NXP 32-bit MCU, Dual Power Arch, 1MB Flash, 120MHz, -40/+125degC, Automotive Grade, QFP 144

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GPC5643LF2MLQ1 数据手册

Introduction

1.5

Feature details

1.5.1

High-performance e200z4d core

The e200z4d Power Architecture core provides the following features:

•

2 independent execution units, both supporting fixed-point and floating-point operations

Dual issue 32-bit Power Architecture technology compliant

— 5-stage pipeline (IF, DEC, EX1, EX2, WB)

— In-order execution and instruction retirement

Full support for Power Architecture instruction set and Variable Length Encoding (VLE)

— Mix of classic 32-bit and 16-bit instruction allowed

— Optimization of code size possible

•

Thirty-two 64-bit general purpose registers (GPRs)

Harvard bus (32-bit address, 64-bit data)

— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return

— D-Bus interface capable of two transactions outstanding to fill AHB pipe

I-cache and I-cache controller

•

— 4 KB, 256-bit cache line (programmable for 2- or 4-way)

No data cache

•

16-entry MMU

8-entry branch table buffer

Branch look-ahead instruction buffer to accelerate branching

Dedicated branch address calculator

3 cycles worst case for missed branch

Load/store unit

— Fully pipelined

— Single-cycle load latency

— Big- and little-endian modes supported

— Misaligned access support

— Single stall cycle on load to use

•

Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication

4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)

Single precision floating-point unit

— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication

— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division

— Special square root and min/max function implemented

Signal processing support: APU-SPE 1.1

•

— Support for vectorized mode: as many as two floating-point instructions per clock

Vectored interrupt support

•

Reservation instruction to support read-modify-write constructs

Extensive system development and tracing support via Nexus debug port

MPC5643L Microcontroller Data Sheet, Rev. 10

NXP Semiconductors

1...4 5 678 9 10...136

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