Datasheet > GPC5643LF2MLQ1

GPC5643LF2MLQ1

更新时间： 2024-03-03 10:07:49

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
136页	1175K
描述
NXP 32-bit MCU, Dual Power Arch, 1MB Flash, 120MHz, -40/+125degC, Automotive Grade, QFP 144

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GPC5643LF2MLQ1 数据手册

Introduction

•

Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a

least-recently-used replacement algorithm to maximize performance.

Programmable response for read-while-write sequences including support for stall-while-write, optional stall

notification interrupt, optional flash operation abort , and optional abort notification interrupt.

Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of

platforms and frequencies.

•

Support of address-based read access timing for emulation of other memory types.

Support for reporting of single- and multi-bit error events.

Typical operating configuration loaded into programming model by system reset.

The platform flash controller is replicated for each processor.

1.5.8

Platform Static RAM Controller (SRAMC)

The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.

The main features of the SRAMC provide connectivity for the following interfaces:

•

XBAR Slave Port (64-bit data path)

ECSM (ECC Error Reporting, error injection and configuration)

SRAM array

The following functions are implemented:

•

ECC encoding (32-bit boundary for data and complete address bus)

ECC decoding (32-bit boundary and entire address)

Address translation from the AHB protocol on the XBAR to the SRAM array

The platform SRAM controller is replicated for each processor.

1.5.9

Memory subsystem access time

Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower

memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the

slave being accessed is not parked on the requesting master in the crossbar.

Table 2 shows the number of additional data phase wait states required for a range of memory accesses.

Table 2. Platform memory access time summary

Data phase

wait states

AHB transfer

Description

e200z4d instruction fetch

Flash memory prefetch buffer hit (page hit)

Flash memory prefetch buffer miss

(based on 4-cycle random flash array access time)

e200z4d data read

e200z4d data write

0–1

SRAM read

SRAM 32-bit write

MPC5643L Microcontroller Data Sheet, Rev. 10

NXP Semiconductors

1...7 8 91011 12 13...136

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与GPC5643LF2MLQ1相关器件

型号	品牌	获取价格	描述	数据表
GPC5668EK0VMG	NXP	获取价格	NXP 32-bit MCU, Power Arch, 2MB Flash, 116MHz, -10/+105degC, Automotive Grade, MAPBGA 208
GPC5668GF1AVMG	NXP	获取价格	NXP 32-bit MCU, Power Arch, 2MB Flash, 116MHz, -40/+105degC, Automotive Grade, MAPBGA 208
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GPC7.3222K63K31TR12	KEMET	获取价格	Film Capacitor, Polyethylene Naphthalate, 63V, 10% +Tol, 10% -Tol, 0.0022uF, Surface Mount
GPC7.3223K100K33TR12	KEMET	获取价格	Film Capacitor, Polyethylene Naphthalate, 100V, 10% +Tol, 10% -Tol, 0.022uF, Surface Mount
GPC71016A	GENERALPLUS	获取价格	4-bit Speech with SPU
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