Datasheet > GM71VS64403ALJ-6

GM71VS64403ALJ-6

更新时间： 2024-01-21 19:14:39

品牌	Logo	应用领域
其他 - ETC		内存集成电路光电二极管动态存储器
页数	文件大小	规格书
25页	398K
描述
x4 EDO Page Mode DRAM

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GM71VS64403ALJ-6 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOJ, SOJ32,.44	Reach Compliance Code：	compliant
风险等级：	5.83	最长访问时间：	60 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-J32
JESD-609代码：	e0	内存密度：	67108864 bit
内存集成电路类型：	EDO DRAM	内存宽度：	4
端子数量：	32	字数：	16777216 words
字数代码：	16000000	最高工作温度：	70 °C
最低工作温度：		组织：	16MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ	封装等效代码：	SOJ32,.44
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	8192	自我刷新：	YES
最大待机电流：	0.0003 A	子类别：	DRAMs
最大压摆率：	0.14 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

GM71VS64403ALJ-6 数据手册

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GM71V64403A

GM71VS64403AL

LG Semicon

Notes:

AC measurements assume tT = 2§ .À

AC initial pause of 200 § Áis required after power up followed by a minimum of eight

initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-

RAS refresh)

Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a

reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is

controlled exclusively by tCAC.

Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a

reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is

controlled exclusively by tAA.

Either tOED or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH(min) and VIL (max).

8. Assumes that tRCD¡ ÂtRCD(max) and tRAD¡ ÂtRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.

10. Assumes that tRCD¡ tÃRCD(max) and tRCD + tCAC(max) ¡ ÃtRAD + tAA(max).

11.

12.

Assumes that tRAD ¡ tÃRAD (max) and tRCD + tCAC(max)¡ tÂRAD + tAA(max).

Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the

open circuit condition and is not referenced to output voltage levels.

14. tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only: if tWCS ¡ tÃWCS(min), the cycle is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if

tRWD ¡ tÃRWD(min), tCWD¡ tÃCWD(min), tAWD¡ tÃAWD(min) and tCPW¡ tÃCPW(min), the cycle is a read-

modify-write and the data output will contain data read from the selected cell: if neither of the

above sets of conditions is satisfied, the condition of the data out (at access time) is

indeterminate.

15.

tDS and tDH are referred to CAS leading edge in early write cycles and to WE leading edge in

delayed write or read-modify-write cycles.

16. tRASP defines RAS pulse width in extended data out mode cycles.

Access time is determined by the longest among tAA, tCAC and tCPA.

17.

18.

In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device.

19.

When output buffers are enabled once, sustain the low impedance state until valid daa is

obtained. When output buffer is turned on and off within a very short time, generally it causes

large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.

1...5 6 789 10 11...25

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